sam3/include/periph_cpu.h

CPU specific definitions for internal peripheral handling.

HAVE_GPIO_T

Overwrite the default gpio_t type definition.

uint32_t gpio_t
PERIPH_SPI_NEEDS_INIT_CS

Declare needed generic SPI functions.

PERIPH_SPI_NEEDS_TRANSFER_BYTE
PERIPH_SPI_NEEDS_TRANSFER_REG
PERIPH_SPI_NEEDS_TRANSFER_REGS
ADC_NUMOF
1
(16U)
DAC_NUMOF

DAC configuration, valid for all boards using this CPU. 

1
(2U)

The sam3 has a fixed mapping of DAC pins and a fixed number of DAC channels, so this DAC configuration is valid for all boards using this CPU. No need for any board specific configuration.

The sam3’s DAC channels are mapped to the following fixed pins:

  • line 0 (ch0): PB15
  • line 1 (ch1): PB16

HAVE_SPI_MODE_T

Override default SPI modes.

enum @80
PA = 0
port A
PB = 1
port B
PC = 2
port C
PD = 3
port D
enum gpio_mux_t
GPIO_MUX_A = 0x0
select peripheral function A
GPIO_MUX_B = 0x1
select peripheral function B
GPIO_MUX_C = 0x2
select peripheral function C
GPIO_MUX_D = 0x3
select peripheral function D
GPIO_MUX_E = 0x4
select peripheral function E
GPIO_MUX_F = 0x5
select peripheral function F
GPIO_MUX_G = 0x6
select peripheral function G
GPIO_MUX_H = 0x7
select peripheral function H
GPIO_MUX_A = 0
alternate function A
GPIO_MUX_B = 1
alternate function B
enum spi_mode_t
SPI_MODE_0 = SPI_MODE_SEL(0, 0)
mode 0
SPI_MODE_1 = SPI_MODE_SEL(0, 1)
mode 1
SPI_MODE_2 = SPI_MODE_SEL(1, 0)
mode 2
SPI_MODE_3 = SPI_MODE_SEL(1, 1)
mode 3
HAVE_SPI_CLK_T

Override default SPI clock values.

enum spi_clk_t
SPI_CLK_4MHZ = 4000000
drive the SPI bus with 4MHz
SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1)
16/128 -> 125KHz
SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0)
16/32 -> 500KHz
SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1)
16/16 -> 1MHz
SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0)
16/4 -> 4MHz
SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)
16/2 -> 8MHz
HAVE_ADC_RES_T

Override ADC resolution values.

enum adc_res_t
ADC_RES_7BIT =             (0 << 4)
ADC resolution: 7 bit.
ADC_RES_9BIT =             (1 << 4)
ADC resolution: 9 bit.
ADC_RES_11BIT
ADC resolution: 11 bit.
ADC_RES_6BIT =             (0xa00)
not supported by hardware
ADC_RES_8BIT =             (0xb00)
not supported by hardware
ADC_RES_10BIT =             (2 << 4)
ADC resolution: 10 bit.
ADC_RES_12BIT =             (3 << 4)
ADC resolution: 12 bit.
ADC_RES_14BIT =             (0xc00)
not supported by hardware
ADC_RES_16BIT =             (0xd00)
not supported by hardware
GPIO_UNDEF

Definition of a fitting UNDEF value. 

1
(0xffffffff)
GPIO_PIN( x, y)

Define a CPU specific GPIO pin generator macro. 

1
(((uint32_t)PIOA + (x << 9)) | y)
CPUID_LEN

Length of the CPU_ID in octets. 

1
(16U)
TIMER_MAX_VAL

All SAM3 timers are 32-bit wide. 

1
(0xffffffff)
TIMER_CHANNELS

We use 3 channels for each defined timer. 

1
(3)
GPIO_MODE( io, pu, od)

Generate GPIO mode bitfields. 

1
(io | (pu << 1) | (od << 2))

We use 3 bit to determine the pin functions:

  • bit 0: in/out
  • bit 1: PU enable
  • bit 2: OD enable

void gpio_init_mux(gpio.h::gpio_t pin, sam0_common/include/periph_cpu_common.h::gpio_mux_t mux)

Configure the given GPIO pin to be used with the given MUX setting.

Parameters

pin:GPIO pin to configure
mux:MUX setting to use

struct timer_conf_t

Timer configuration.

Timer configuration data.

Timer configuration options.

Define timer configuration values.

General purpose timers (GPT[0-3]) are configured consecutively and in order (without gaps) starting from GPT0, i.e. if multiple timers are enabled.

Note

The two timers must be adjacent to each other (e.g. TIMER0 and TIMER1, or TIMER2 and TIMER3, etc.).

uint_fast8_t chn

number of channels

uint_fast8_t cfg

timer config word

timer_dev_t prescaler

the lower numbered neighboring timer

timer_dev_t timer

the higher numbered timer

cc2538.h::IRQn_Type irq

number of the higher timer IRQ channel

TIMER_TypeDef * prescaler

the lower numbered neighboring timer

TIMER_TypeDef * timer

the higher numbered timer

uint8_t pre_cmu

prescale timer bit in CMU register, the timer bit is deducted from this

uint8_t irqn

number of the higher timer IRQ channel

global IRQ channel

IRQ number of the timer device.

NRF_TIMER_Type * dev

timer device

uint8_t channels

number of channels available

uint8_t bitmode

counter width

Tc * dev

timer device

uint8_t id_ch0

ID of the timer’s first channel.

TIM_TypeDef * dev

timer device

uint32_t max

maximum value to count to (16/32 bit)

uint32_t rcc_mask

corresponding bit in the RCC register

uint8_t bus

APBx bus the timer is clock from.

struct uart_conf_t

UART device configuration.

Structure for UART configuration data.

UART configuration data.

UART module configuration options.

cc2538_uart_t * dev

pointer to the used UART device

UART device base register address.

Pointer to module hardware registers.

gpio.h::gpio_t rx_pin

pin used for RX

RX pin.

Pin used for RX.

gpio.h::gpio_t tx_pin

pin used for TX

TX pin.

Pin used for TX.

gpio.h::gpio_t cts_pin

CTS pin - set to GPIO_UNDEF when not using.

gpio.h::gpio_t rts_pin

RTS pin - set to GPIO_UNDEF when not using.

void * dev

UART, USART or LEUART device used.

Pointer to module hardware registers.

uint32_t loc

location of UART pins

CMU_Clock_TypeDef cmu

the device CMU channel

cc2538.h::IRQn_Type irq

the devices base IRQ channel

USART_TypeDef * dev

USART device used.

UART device base register address.

uint8_t loc

location of USART pins (AF)

uint8_t cmu

the device CMU channel

uint8_t irq

the devices base IRQ channel

uint32_t freq

Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.

gpio.h::gpio_t pin_rx

RX pin, GPIO_UNDEF disables RX.

gpio.h::gpio_t pin_tx

TX pin.

uint32_t pcr_rx

Pin configuration register bits for RX.

uint32_t pcr_tx

Pin configuration register bits for TX.

uint32_t * scgc_addr

Clock enable register, in SIM module.

uint8_t scgc_bit

Clock enable bit, within the register.

kinetis/include/periph_cpu.h::uart_mode_t mode

UART mode: data bits, parity, stop bits.

kinetis/include/periph_cpu.h::uart_type_t type

Hardware module type (KINETIS_UART or KINETIS_LPUART)

SercomUsart * dev

pointer to the used UART device

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

alternative function for pins

MUX used for pins.

sam0_common/include/periph_cpu_common.h::uart_rxpad_t rx_pad

pad selection for RX line

sam0_common/include/periph_cpu_common.h::uart_txpad_t tx_pad

pad selection for TX line

sam0_common/include/periph_cpu_common.h::uart_flag_t flags

set optional SERCOM flags

uint32_t gclk_src

GCLK source which supplys SERCOM.

Uart * dev

U(S)ART device used.

uint8_t pmc_id

bit in the PMC register of the device

cc2538.h::IRQn_Type irqn

IRQ number for this module.

IRQ channel.

uint32_t rcc_mask

bit in clock enable register

stm32_common/include/periph_cpu_common.h::gpio_af_t rx_af

alternate function for RX pin

stm32_common/include/periph_cpu_common.h::gpio_af_t tx_af

alternate function for TX pin

uint8_t bus

APB bus.

struct pwm_chan_conf_t

PWM channel configuration.

PWM channel configuration data.

uint8_t index

TIMER channel to use.

gpio.h::gpio_t pin

pin used for pwm

GPIO pin connected to the channel.

uint32_t loc

location of the pin

uint8_t hwchan

the HW channel used for a logical channel

struct spi_conf_t

SPI module configuration options.

Structure for SPI configuration data.

SPI configuration data.

SPI device configuration.

SPI configuration values.

SPI configuration data structure.

uint8_t num

number of SSI device, i.e.

0 or 1

gpio.h::gpio_t mosi_pin

pin used for MOSI

MOSI pin.

used MOSI pin

gpio.h::gpio_t miso_pin

pin used for MISO

MISO pin.

used MISO pin

gpio.h::gpio_t sck_pin

pin used for SCK

gpio.h::gpio_t cs_pin

pin used for CS

HWCS pin, set to GPIO_UNDEF if not mapped.

SPI_Type * dev

SPI device to use.

gpio.h::gpio_t pin_miso

MISO pin used.

gpio.h::gpio_t pin_mosi

MOSI pin used.

gpio.h::gpio_t pin_clk

CLK pin used.

gpio.h::gpio_t pin_cs()

pins used for HW cs lines

kinetis/include/periph_cpu.h::gpio_pcr_t pcr

alternate pin function values

uint32_t simmask

bit in the SIM register

unsigned long ssi_sysctl

SSI device in sysctl.

unsigned long ssi_base

SSI base address.

unsigned long gpio_sysctl

GPIO device in sysctl.

unsigned long gpio_port

GPIO port.

unsigned long clk

pin used for SCK

unsigned long fss

pin used for FSS

unsigned long rx

pin used for MISO

unsigned long tx

pin used for MOSI

unsigned long mask

Pin mask.

struct spi_conf_t::@74 pins

Pin setting.

NRF_SPI_Type * dev

SPI device used.

uint8_t sclk

CLK pin.

uint8_t mosi

MOSI pin.

uint8_t miso

MISO pin.

SercomSpi * dev

pointer to the used SPI device

gpio.h::gpio_t clk_pin

used CLK pin

sam0_common/include/periph_cpu_common.h::gpio_mux_t miso_mux

alternate function for MISO pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t mosi_mux

alternate function for MOSI pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t clk_mux

alternate function for CLK pin (mux)

sam0_common/include/periph_cpu_common.h::spi_misopad_t miso_pad

pad to use for MISO line

sam0_common/include/periph_cpu_common.h::spi_mosipad_t mosi_pad

pad to use for MOSI and CLK line

Spi * dev

SPI module to use.

uint8_t id

corresponding ID of that module

gpio.h::gpio_t clk

pin mapped to the CLK line

gpio.h::gpio_t mosi

pin mapped to the MOSI line

gpio.h::gpio_t miso

pin mapped to the MISO line

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

pin MUX setting

SPI_TypeDef * dev

SPI device base register address.

gpio.h::gpio_t sclk_pin

SCLK pin.

stm32_common/include/periph_cpu_common.h::gpio_af_t af

pin alternate function

uint32_t rccmask

bit in the RCC peripheral enable register

uint8_t apbbus

APBx bus the device is connected to.