enc28j60_regs.h

Register definitions for the ENC28J60 Ethernet device.

CMD_RCR
1
0x00            /* read control register */
CMD_RBM
1
0x3a            /* read buffer memory */
CMD_WCR
1
0x40            /* write control register */
CMD_WBM
1
0x7a            /* write buffer memory */
CMD_BFS
1
0x80            /* bit field set */
CMD_BFC
1
0xa0            /* bit field clear */
CMD_SRC
1
0xff            /* system reset command (soft reset) */
ADDR_READ_PTR

Read pointer. 

1
0x00
ADDR_WRITE_PTR

Write data pointer. 

1
0x02
ADDR_TX_START

TX buffer start. 

1
0x04
ADDR_TX_END

TX buffer end. 

1
0x06
ADDR_RX_START

RX buffer start. 

1
0x08
ADDR_RX_END

RX buffer end. 

1
0x0a
ADDR_RX_READ

start of oldest packet in RX buffer 

1
0x0c
ADDR_RX_WRITE

start of free space in RX buffer 

1
0x0e
REG_EIE

interrupt enable 

1
0x1b
REG_EIR

interrupt flags 

1
0x1c
REG_ESTAT

status 

1
0x1d
REG_ECON2

configuration 1 

1
0x1e
REG_ECON1

configuration 2 

1
0x1f
REG_B0_ERDPTL
1
0x00    /* read data pointer - low byte */
REG_B0_ERDPTH
1
0x01    /* read data pointer - high byte */
REG_B0_EWRPTL
1
0x02    /* write data pointer - low byte */
REG_B0_EWRPTH
1
0x03    /* write data pointer - high byte */
REG_B0_ETXSTL
1
0x04    /* TX start pointer - low byte */
REG_B0_ETXSTH
1
0x05    /* TX start pointer - high byte */
REG_B0_ETXNDL
1
0x06    /* TX end pointer - low byte */
REG_B0_ETXNDH
1
0x07    /* TX end pointer - high byte */
REG_B0_ERXSTL
1
0x08    /* RX start pointer - low byte */
REG_B0_ERXSTH
1
0x09    /* RX start pointer - high byte */
REG_B0_ERXNDL
1
0x0a    /* RX end pointer - low byte */
REG_B0_ERXNDH
1
0x0b    /* RX end pointer - high byte */
REG_B0_ERXRDPTL
1
0x0c    /* RX read pointer - low byte */
REG_B0_ERXRDPTH
1
0x0d    /* RX read pointer - high byte */
REG_B0_ERXWRPTL
1
0x0e    /* RX write pointer - low byte */
REG_B0_ERXWRPTH
1
0x0f    /* RX write pointer - high byte */
REG_B0_EDMASTL
1
0x10    /* DMA start pointer - low byte */
REG_B0_EDMASTH
1
0x11    /* DMA start pointer - high byte */
REG_B0_EDMANDL
1
0x12    /* DMA end pointer - low byte */
REG_B0_EDMANDH
1
0x13    /* DMA end pointer - high byte */
REG_B0_EDMADSTL
1
0x14    /* DMA destination pointer - low byte */
REG_B0_EDMADSTH
1
0x15    /* DMA destination pointer - high byte */
REG_B0_EDMACSL
1
0x16    /* DMA checksum - low byte */
REG_B0_EDMACSH
1
0x17    /* DMA checksum - high byte */
REG_B1_EHT0
1
0x00    /* hash table - byte 0 */
REG_B1_EHT1
1
0x01    /* hash table - byte 1 */
REG_B1_EHT2
1
0x02    /* hash table - byte 2 */
REG_B1_EHT3
1
0x03    /* hash table - byte 3 */
REG_B1_EHT4
1
0x04    /* hash table - byte 4 */
REG_B1_EHT5
1
0x05    /* hash table - byte 5 */
REG_B1_EHT6
1
0x06    /* hash table - byte 6 */
REG_B1_EHT7
1
0x07    /* hash table - byte 7 */
REG_B1_EPMM0
1
0x08    /* pattern match mask - byte 0 */
REG_B1_EPMM1
1
0x09    /* pattern match mask - byte 1 */
REG_B1_EPMM2
1
0x0a    /* pattern match mask - byte 2 */
REG_B1_EPMM3
1
0x0b    /* pattern match mask - byte 3 */
REG_B1_EPMM4
1
0x0c    /* pattern match mask - byte 4 */
REG_B1_EPMM5
1
0x0d    /* pattern match mask - byte 5 */
REG_B1_EPMM6
1
0x0e    /* pattern match mask - byte 6 */
REG_B1_EPMM7
1
0x0f    /* pattern match mask - byte 7 */
REG_B1_EPMCSL
1
0x10    /* pattern match checksum - low byte */
REG_B1_EPMCSH
1
0x11    /* pattern match checksum - high byte */
REG_B1_EPMOL
1
0x14    /* pattern match offset - low byte */
REG_B1_EPMOH
1
0x15    /* pattern match offset - high byte */
REG_B1_ERXFCON
1
0x18    /* receive filter control register */
REG_B1_EPKTCNT
1
0x19    /* packet count */
REG_B2_MACON1
1
0x00    /* MAC control register 1 */
REG_B2_MACON3
1
0x02    /* MAC control register 3 */
REG_B2_MACON4
1
0x03    /* MAC control register 4 */
REG_B2_MABBIPG
1
0x04    /* back-to-back inter-packet gap */
REG_B2_MAIPGL
1
0x06    /* non-back-to-back inter-packet gap - low byte */
REG_B2_MAIPGH
1
0x07    /* non-back-to-back inter-packet gap - high byte */
REG_B2_MACLCON1
1
0x08    /* retransmission maximum */
REG_B2_MACLCON2
1
0x09    /* collision window */
REG_B2_MAMXFLL
1
0x0a    /* maximum frame length - low byte */
REG_B2_MAMXFLH
1
0x0b    /* maximum frame length - high byte */
REG_B2_MICMD
1
0x12    /* MIIM command */
REG_B2_MIREGADR
1
0x14    /* MIIM register address */
REG_B2_MIWRL
1
0x16    /* MIIM write data register - low byte */
REG_B2_MIWRH
1
0x17    /* MIIM write data register - high byte */
REG_B2_MIRDL
1
0x18    /* MIIM read data register - low byte */
REG_B2_MIRDH
1
0x19    /* MIIM read data register - high byte */
REG_B3_MAADR5
1
0x00    /* MAC address - byte 5 */
REG_B3_MAADR6
1
0x01    /* MAC address - byte 6 */
REG_B3_MAADR3
1
0x02    /* MAC address - byte 3 */
REG_B3_MAADR4
1
0x03    /* MAC address - byte 4 */
REG_B3_MAADR1
1
0x04    /* MAC address - byte 1 */
REG_B3_MAADR2
1
0x05    /* MAC address - byte 2 */
REG_B3_EBSTSD
1
0x06    /* built-in self-test fill seed */
REG_B3_EBSTCON
1
0x07    /* built-in self-test control register */
REG_B3_EBSTCSL
1
0x08    /* built-in self-test checksum - low byte */
REG_B3_EBSTCSH
1
0x09    /* built-in self-test checksum - high byte */
REG_B3_MISTAT
1
0x0a    /* MIIM status register */
REG_B3_EREVID
1
0x12    /* Ethernet revision ID */
REG_B3_ECOCON
1
0x15    /* clock output control */
REG_B3_EFLOCON
1
0x17    /* Ethernet flow control */
REG_B3_EPAUSL
1
0x18    /* pause timer value - low byte */
REG_B3_EPAUSH
1
0x19    /* pause timer value - high byte */
REG_PHY_PHCON1
1
0x00
REG_PHY_PHSTAT1
1
0x01
REG_PHY_PHID1
1
0x02
REG_PHY_PHID2
1
0x03
REG_PHY_PHCON2
1
0x10
REG_PHY_PHSTAT2
1
0x11
REG_PHY_PHIE
1
0x12
REG_PHY_PHIR
1
0x13
REG_PHY_PHLCON
1
0x14
EIE_INTIE
1
0x80
EIE_PKTIE
1
0x40
EIE_DMAIE
1
0x20
EIE_LINKIE
1
0x10
EIE_TXIE
1
0x08
EIE_TXERIE
1
0x02
EIE_RXERIE
1
0x01
EIR_PKTIF
1
0x40
EIR_DMAIF
1
0x20
EIR_LINKIF
1
0x10
EIR_TXIF
1
0x08
EIR_TXERIF
1
0x02
EIR_RXERIF
1
0x01
ESTAT_INT
1
0x80
ESTAT_BUFFER
1
0x40
ESTAT_LATECOL
1
0x10
ESTAT_RXBUSY
1
0x40
ESTAT_TXABRT
1
0x20
ESTAT_CLKRDY
1
0x01
ECON1_TXRST
1
0x80
ECON1_RXRST
1
0x40
ECON1_DMAST
1
0x20
ECON1_CSUMEN
1
0x10
ECON1_TXRTS
1
0x08
ECON1_RXEN
1
0x04
ECON1_BSEL1
1
0x02
ECON1_BSEL0
1
0x01
ECON1_BSEL_MASK
1
0x03
ECON2_AUTOINC
1
0x80
ECON2_PKTDEC
1
0x40
ECON2_PWRSV
1
0x20
ECON2_VRPS
1
0x40
ERXFCON_UCEN
1
0x80
ERXFCON_ANDOR
1
0x40
ERXFCON_CRCEN
1
0x20
ERXFCON_PMEN
1
0x10
ERXFCON_MPEN
1
0x08
ERXFCON_HTEN
1
0x04
ERXFCON_MCEN
1
0x02
ERXFCON_BCEN
1
0x01
MACON1_TXPAUS
1
0x08
MACON1_RXPAUS
1
0x04
MACON1_PASSALL
1
0x02
MACON1_MARXEN
1
0x01
MACON3_PADCFG2
1
0x80
MACON3_PADCFG1
1
0x40
MACON3_PADCFG0
1
0x20
MACON3_TXCRCEN
1
0x10
MACON3_PHDREN
1
0x08
MACON3_HFRMEN
1
0x04
MACON3_FRMLNEN
1
0x02
MACON3_FULDPX
1
0x01
MACON4_DEFER
1
0x40
MACON4_BPEN
1
0x20
MACON4_NOBKOFF
1
0x10
MABBIPG_FD
1
0x15
MABBIPG_HD
1
0x12
MAIPGL_FD
1
0x12
MICMD_MIISCAN
1
0x02
MICMD_MIIRD
1
0x01
MISTAT_NVALID
1
0x04
MISTAT_SCAN
1
0x02
MISTAT_BUSY
1
0x01
EFLOCON_FULDPXS
1
0x04
EFLOCON_FCEN1
1
0x02
EFLOCON_FCEN0
1
0x01
EFLOCON_FCEN_MASK
1
0x03
PHCON1_PRST
1
0x8000
PHCON1_PLOOPBK
1
0x4000
PHCON1_PPWRSV
1
0x0800
PHCON1_PDPXMD
1
0x0100
PHSTAT1_PFDPX
1
0x1000
PHSTAT1_PHDPX
1
0x0800
PHSTAT1_LLSTAT
1
0x0004
PHSTAT1_JBSTAT
1
0x0002
PHCON2_FRCLNK
1
0x4000
PHCON2_TXDIS
1
0x2000
PHCON2_JABBER
1
0x0400
PHCON2_HDLDIS
1
0x0100
PHSTAT2_TXSTAT
1
0x2000
PHSTAT2_RXSTAT
1
0x1000
PHSTAT2_COLSTAT
1
0x0800
PHSTAT2_LSTAT
1
0x0400
PHSTAT2_DPXSTAT
1
0x0200
PHSTAT2_PLRITY
1
0x0020
PHIE_PLNKIE
1
0x0010
PHIE_PGEIE
1
0x0002
PHIR_PLNKIF
1
0x0010
PHIR_PGIF
1
0x0004
PHLCON_LACFG( x)
1
((x & 0xf) << 8)
PHLCON_LBCFG( x)
1
((x & 0xf) << 4)
PHLCON_LFRQ( x)
1
((x & 0x3) << 2)
PHLCON_STRCH
1
0x0002
FRAME_4_RECV_OK
1
0x80
FRAME_4_LENGTH_OOR
1
0x40
FRAME_4_LENGTH_ERR
1
0x20
FRAME_4_CRC_ERR
1
0x10
FRAME_4_CARRIER_EVT
1
0x04
FRAME_4_LONG_EVT
1
0x01
FRAME_5_VLAN
1
0x40
FRAME_5_UKWN_OPCODE
1
0x20
FRAME_5_PAUSE
1
0x10
FRAME_5_RCV_CTRL
1
0x08
FRAME_5_DRIPPLE
1
0x04
FRAME_5_BCAST
1
0x02
FRAME_5_MCAST
1
0x01
TX_PHUGEEN
1
0x08
TX_PPADEN
1
0x04
TX_PCRCEN
1
0x02
TX_POVERRIDE
1
0x01