nrf5x_common/include/periph_cpu_common.h

nRF5x common definitions for handling peripherals

PROVIDES_PM_OFF
GPIO_PIN( x, y)
1
((x & 0) | y)
GPIO_UNDEF

Override GPIO_UNDEF value. 

1
(UINT_MAX)
GPIO_MODE( oe, ic, pr)

Generate GPIO mode bitfields. 

1
(oe | (ic << 1) | (pr << 2))

We use 4 bit to encode the pin mode:

  • bit 0: output enable
  • bit 1: input connect
  • bit 2+3: pull resistor configuration

SPI_HWCS( x)

No support for HW chip select… 

1
(SPI_CS_UNDEF)
PERIPH_SPI_NEEDS_INIT_CS

Declare needed shared SPI functions.

PERIPH_SPI_NEEDS_TRANSFER_BYTE
PERIPH_SPI_NEEDS_TRANSFER_REG
PERIPH_SPI_NEEDS_TRANSFER_REGS
HAVE_SPI_MODE_T

Override SPI mode values.

enum spi_mode_t
SPI_MODE_0 = SPI_MODE_SEL(0, 0)
mode 0
SPI_MODE_1 = SPI_MODE_SEL(0, 1)
mode 1
SPI_MODE_2 = SPI_MODE_SEL(1, 0)
mode 2
SPI_MODE_3 = SPI_MODE_SEL(1, 1)
mode 3
HAVE_SPI_CLK_T

Override SPI clock values.

enum spi_clk_t
SPI_CLK_4MHZ = 4000000
drive the SPI bus with 4MHz
SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1)
16/128 -> 125KHz
SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0)
16/32 -> 500KHz
SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1)
16/16 -> 1MHz
SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0)
16/4 -> 4MHz
SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)
16/2 -> 8MHz
CPUID_ADDR

Starting offset of CPU_ID. 

1
(&NRF_FICR->DEVICEID[0])
CPUID_LEN

Length of the CPU_ID in octets. 

1
(8U)
struct timer_conf_t

Timer configuration.

Timer configuration data.

Timer configuration options.

Define timer configuration values.

General purpose timers (GPT[0-3]) are configured consecutively and in order (without gaps) starting from GPT0, i.e. if multiple timers are enabled.

Note

The two timers must be adjacent to each other (e.g. TIMER0 and TIMER1, or TIMER2 and TIMER3, etc.).

uint_fast8_t chn

number of channels

uint_fast8_t cfg

timer config word

timer_dev_t prescaler

the lower numbered neighboring timer

timer_dev_t timer

the higher numbered timer

cc2538.h::IRQn_Type irq

number of the higher timer IRQ channel

TIMER_TypeDef * prescaler

the lower numbered neighboring timer

TIMER_TypeDef * timer

the higher numbered timer

uint8_t pre_cmu

prescale timer bit in CMU register, the timer bit is deducted from this

uint8_t irqn

number of the higher timer IRQ channel

global IRQ channel

IRQ number of the timer device.

NRF_TIMER_Type * dev

timer device

uint8_t channels

number of channels available

uint8_t bitmode

counter width

Tc * dev

timer device

uint8_t id_ch0

ID of the timer’s first channel.

TIM_TypeDef * dev

timer device

uint32_t max

maximum value to count to (16/32 bit)

uint32_t rcc_mask

corresponding bit in the RCC register

uint8_t bus

APBx bus the timer is clock from.

struct spi_conf_t

SPI module configuration options.

Structure for SPI configuration data.

SPI configuration data.

SPI device configuration.

SPI configuration values.

SPI configuration data structure.

uint8_t num

number of SSI device, i.e.

0 or 1

gpio.h::gpio_t mosi_pin

pin used for MOSI

MOSI pin.

used MOSI pin

gpio.h::gpio_t miso_pin

pin used for MISO

MISO pin.

used MISO pin

gpio.h::gpio_t sck_pin

pin used for SCK

gpio.h::gpio_t cs_pin

pin used for CS

HWCS pin, set to GPIO_UNDEF if not mapped.

SPI_Type * dev

SPI device to use.

gpio.h::gpio_t pin_miso

MISO pin used.

gpio.h::gpio_t pin_mosi

MOSI pin used.

gpio.h::gpio_t pin_clk

CLK pin used.

gpio.h::gpio_t pin_cs()

pins used for HW cs lines

kinetis/include/periph_cpu.h::gpio_pcr_t pcr

alternate pin function values

uint32_t simmask

bit in the SIM register

unsigned long ssi_sysctl

SSI device in sysctl.

unsigned long ssi_base

SSI base address.

unsigned long gpio_sysctl

GPIO device in sysctl.

unsigned long gpio_port

GPIO port.

unsigned long clk

pin used for SCK

unsigned long fss

pin used for FSS

unsigned long rx

pin used for MISO

unsigned long tx

pin used for MOSI

unsigned long mask

Pin mask.

struct spi_conf_t::@74 pins

Pin setting.

NRF_SPI_Type * dev

SPI device used.

uint8_t sclk

CLK pin.

uint8_t mosi

MOSI pin.

uint8_t miso

MISO pin.

SercomSpi * dev

pointer to the used SPI device

gpio.h::gpio_t clk_pin

used CLK pin

sam0_common/include/periph_cpu_common.h::gpio_mux_t miso_mux

alternate function for MISO pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t mosi_mux

alternate function for MOSI pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t clk_mux

alternate function for CLK pin (mux)

sam0_common/include/periph_cpu_common.h::spi_misopad_t miso_pad

pad to use for MISO line

sam0_common/include/periph_cpu_common.h::spi_mosipad_t mosi_pad

pad to use for MOSI and CLK line

Spi * dev

SPI module to use.

uint8_t id

corresponding ID of that module

gpio.h::gpio_t clk

pin mapped to the CLK line

gpio.h::gpio_t mosi

pin mapped to the MOSI line

gpio.h::gpio_t miso

pin mapped to the MISO line

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

pin MUX setting

SPI_TypeDef * dev

SPI device base register address.

gpio.h::gpio_t sclk_pin

SCLK pin.

stm32_common/include/periph_cpu_common.h::gpio_af_t af

pin alternate function

uint32_t rccmask

bit in the RCC peripheral enable register

uint8_t apbbus

APBx bus the device is connected to.