kinetis/include/periph_cpu.h

CPU specific definitions for internal peripheral handling.

HAVE_GPIO_T
uint16_t gpio_t
PERIPH_SPI_NEEDS_TRANSFER_BYTE
1
1
PERIPH_SPI_NEEDS_TRANSFER_REG
1
1
PERIPH_SPI_NEEDS_TRANSFER_REGS
1
1
TIMER_PIT_DEV( x)

Timers using PIT backend. 

1
(TIMER_DEV(0 + (x)))
TIMER_LPTMR_DEV( x)

Timers using LPTMR backend. 

1
(TIMER_DEV(PIT_NUMOF + (x)))
GPIO_UNDEF

Definition of a fitting UNDEF value. 

1
(0xffff)
GPIO_PIN( x, y)

Define a CPU specific GPIO pin generator macro. 

1
(((x + 1) << 12) | (x << 6) | y)
CPUID_ADDR

Starting offset of CPU_ID. 

1
(&SIM->UIDMH)
CPUID_LEN

Length of the CPU_ID in octets. 

1
(12U)
GPIO_MODE( pu, pe, od, out)

Generate GPIO mode bitfields. 

1
(pu | (pe << 1) | (od << 5) | (out << 7))

We use the following bits to encode the pin mode:

  • bit 0: 0 for pull-down or 1 for pull-up
  • bit 1: pull resistor enable (as configured in bit 0)
  • bit 5: OD enable
  • bit 7: output or input mode

SPI_HWCS( x)

Define a CPU specific SPI hardware chip select line macro. 

1
(x)

We simply map the 5 hardware channels to the numbers [0-4], this still allows us to differentiate between GPIP_PINs and SPI_HWSC lines.

SPI_HWCS_NUMOF

Kinetis CPUs have a maximum number of 5 hardware chip select lines. 

1
(5)
PERIPH_TIMER_PROVIDES_SET

Prevent shared timer functions from being used.

PM_NUM_MODES

number of usable power modes 

1
(1U)
ADC_AVG_NONE

Disable hardware averaging. 

1
(0)
ADC_AVG_MAX

Maximum hardware averaging (32 samples) 

1
(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
KINETIS_HAVE_PLL

Defined to 1 if the MCG in this Kinetis CPU has a PLL. 

1
1
enum gpio_pcr_t
GPIO_AF_ANALOG = PORT_PCR_MUX(0)
use pin as analog input
GPIO_AF_GPIO = PORT_PCR_MUX(1)
use pin as GPIO
GPIO_AF_2 = PORT_PCR_MUX(2)
use alternate function 2
GPIO_AF_3 = PORT_PCR_MUX(3)
use alternate function 3
GPIO_AF_4 = PORT_PCR_MUX(4)
use alternate function 4
GPIO_AF_5 = PORT_PCR_MUX(5)
use alternate function 5
GPIO_AF_6 = PORT_PCR_MUX(6)
use alternate function 6
GPIO_AF_7 = PORT_PCR_MUX(7)
use alternate function 7
GPIO_PCR_PD = (PORT_PCR_PE_MASK)
enable pull-down
GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
enable PU
enum @71
PORT_A = 0
port A
PORT_B = 1
port B
PORT_C = 2
port C
PORT_D = 3
port D
PORT_E = 4
port E
PORT_F = 5
port F
PORT_G = 6
port G
GPIO_PORTS_NUMOF
overall number of available ports
enum uart_mode_t
UART_MODE_8N1 = 0
8 data bits, no parity, 1 stop bit
UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK)
8 data bits, even parity, 1 stop bit
UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK)
8 data bits, odd parity, 1 stop bit
enum @72
TIMER_PIT
PIT.
TIMER_LPTMR
LPTMR.
enum uart_type_t
KINETIS_UART
Kinetis UART module type.
KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
enum kinetis_mcg_mode
KINETIS_MCG_MODE_FEI = 0
FLL Engaged Internal Mode.
KINETIS_MCG_MODE_FEE = 1
FLL Engaged External Mode.
KINETIS_MCG_MODE_FBI = 2
FLL Bypassed Internal Mode.
KINETIS_MCG_MODE_FBE = 3
FLL Bypassed External Mode.
KINETIS_MCG_MODE_BLPI = 4
FLL Bypassed Low Power Internal Mode.
KINETIS_MCG_MODE_BLPE = 5
FLL Bypassed Low Power External Mode.
KINETIS_MCG_MODE_PBE = 6
PLL Bypassed External Mode.
KINETIS_MCG_MODE_PEE = 7
PLL Engaged External Mode.
KINETIS_MCG_MODE_NUMOF
Number of possible modes.
enum kinetis_mcg_fll_t
KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0))
FLL multiplier = 640.
KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK)
FLL multiplier = 732.
KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1))
FLL multiplier = 1280.
KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK)
FLL multiplier = 1464.
KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2))
FLL multiplier = 1920.
KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK)
FLL multiplier = 2197.
KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3))
FLL multiplier = 2560.
KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK)
FLL multiplier = 2929.
enum kinetis_mcg_erc_range_t
KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0)
for 31.25-39.0625 kHz crystal
KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1)
for 3-8 MHz crystal
KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2)
for 8-32 MHz crystal
enum kinetis_clock_flags_t
KINETIS_CLOCK_OSC0_EN = (1 <<  0)

Turn on OSC0 oscillator.

  • If this flag is set, the OSC0 oscillator expects a crystal between the pins XTAL0 and EXTAL0, and the OSCCLK internal signal will be provided by OSC0.
  • If not set, the EXTAL0 pin will be used directly as the OSCCLK signal.

KINETIS_CLOCK_RTCOSC_EN = (1 <<  1)

Turn on RTC oscillator.

  • If this flag is set, the RTC oscillator expects a crystal between the pins XTAL32 and EXTAL32.
  • If not set, the EXTAL32 pin can be used as an external clock signal on certain CPU models.

KINETIS_CLOCK_USE_FAST_IRC = (1 <<  2)

Use the fast internal reference clock as MCGIRCLK signal.

This flag corresponds to the IRCS bit in the MCG_C2 register.

Note

This flag affects the clock frequency of the CPU when using the MCG in FBI, or BLPI clocking modes.

  • If this flag is set, the fast internal reference clock (up to 4 MHz, depends on settings) will be routed to the MCGIRCLK internal clock signal.
  • If not set, the slow internal reference clock (32 kHz) will be routed to the MCGIRCLK internal clock signal. FBI and BLPI modes will clock the core at 32 kHz.

KINETIS_CLOCK_MCGIRCLK_EN = (1 <<  3)

Enable MCGIRCLK internal clock signal.

This flag corresponds to the IRCLKEN bit in the MCG_C1 register.

  • If this flag is set, the MCG will provide MCGIRCLK for use by other peripherals.

KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 <<  4)

Enable MCGIRCLK signal during STOP modes.

This flag corresponds to the IREFSTEN bit in the MCG_SC register.

  • If this flag is set, MCGIRCLK internal clock signal will be available for clocking peripherals during CPU STOP modes.
  • If not set, the MCGIRCLK internal clock signal will be stopped during CPU STOP modes.

enum kinetis/include/periph_cpu.h::kinetis_mcg_mode kinetis_mcg_mode_t

Kinetis possible MCG modes.

void gpio_init_port(gpio.h::gpio_t pin, uint32_t pcr)

CPU internal function for initializing PORTs.

Parameters

pin:pin to initialize
pcr:value for the PORT’s PCR register

struct adc_conf_t

ADC device configuration.

Available number of ADC devices.

ADC channel configuration data.

ADC line configuration values.

CPU specific ADC configuration.

ADC channel configuration data

CMU_Clock_TypeDef cmu

the device CMU channel

ADC_Type * dev

ADC module.

gpio.h::gpio_t pin

pin to use

pin connected to the channel

Use GPIO_UNDEF non-muxed ADC pins, e.g. ADC0_DP, or for internal channels, e.g. Bandgap

uint8_t chan

ADC channel.

CPU ADC channel connected to the pin.

internal channel the pin is connected to

Written as-is to ADCx_SC1x before conversion. This also decides single-ended or differential sampling, see CPU reference manual for ADCx_SC1x

uint8_t avg

Hardware averaging configuration.

Written as-is to ADCx_SC3 before conversion, use kinetis/include/periph_cpu.h::ADC_AVG_NONE and kinetis/include/periph_cpu.h::ADC_AVG_MAX as a shorthand notation in the board configuration

ADC_TypeDef * dev

ADC device used.

ADCx - 1 device used for the channel.

struct pit_conf_t

CPU specific timer PIT module configuration.

uint8_t prescaler_ch

Prescaler channel.

uint8_t count_ch

Counting channel, will be linked to the prescaler channel.

struct lptmr_conf_t

CPU specific timer LPTMR module configuration.

LPTMR_Type * dev

LPTMR device base pointer.

uint32_t base_freq

Input clock frequency.

uint8_t src

Clock source setting.

uint8_t irqn

IRQn interrupt number.

struct i2c_conf_t

I2C configuration options.

Structure for I2C configuration data.

I2C (TWI) configuration options.

I2C configuration structure.

I2C device configuration.

cc2538/include/periph_cpu.h::i2c_speed_t speed

baudrate used for the bus

i2c bus speed

Bus speed.

bus speed

Configured bus speed, actual speed may be lower but never higher.

gpio.h::gpio_t scl_pin

pin used for SCL

scl pin number

used SCL pin

SCL GPIO pin.

gpio.h::gpio_t sda_pin

pin used for SDA

sda pin number

used MOSI pin

SDA GPIO pin.

I2C_TypeDef * dev

USART device used.

i2c device

uint32_t loc

location of I2C pins

CMU_Clock_TypeDef cmu

the device CMU channel

cc2538.h::IRQn_Type irq

the devices base IRQ channel

uint32_t speed

the bus speed

I2C_Type * i2c

Pointer to hardware module registers.

uint32_t freq

I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.

cc2538.h::IRQn_Type irqn

IRQ number for this module.

uint32_t scl_pcr

PORT module PCR setting for the SCL pin.

uint32_t sda_pcr

PORT module PCR setting for the SDA pin.

NRF_TWI_Type * dev

hardware device

uint8_t pin_scl

SCL pin.

uint8_t pin_sda

SDA pin.

uint8_t ppi

PPI channel to use.

NRF_TWIM_Type * dev

TWIM hardware device.

uint8_t scl

SCL pin.

uint8_t sda

SDA pin.

SercomI2cm * dev

pointer to the used I2C device

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

alternate function (mux)

uint8_t gclk_src

GCLK source which supplys SERCOM.

uint8_t flags

allow SERCOM to run in standby mode

stm32_common/include/periph_cpu_common.h::gpio_af_t scl_af

scl pin alternate function value

stm32_common/include/periph_cpu_common.h::gpio_af_t sda_af

sda pin alternate function value

uint8_t bus

APB bus.

uint32_t rcc_mask

bit in clock enable register

uint8_t irqn

I2C event interrupt number.

struct spi_conf_t

SPI module configuration options.

Structure for SPI configuration data.

SPI configuration data.

SPI device configuration.

SPI configuration values.

SPI configuration data structure.

uint8_t num

number of SSI device, i.e.

0 or 1

gpio.h::gpio_t mosi_pin

pin used for MOSI

MOSI pin.

used MOSI pin

gpio.h::gpio_t miso_pin

pin used for MISO

MISO pin.

used MISO pin

gpio.h::gpio_t sck_pin

pin used for SCK

gpio.h::gpio_t cs_pin

pin used for CS

HWCS pin, set to GPIO_UNDEF if not mapped.

SPI_Type * dev

SPI device to use.

gpio.h::gpio_t pin_miso

MISO pin used.

gpio.h::gpio_t pin_mosi

MOSI pin used.

gpio.h::gpio_t pin_clk

CLK pin used.

gpio.h::gpio_t pin_cs()

pins used for HW cs lines

kinetis/include/periph_cpu.h::gpio_pcr_t pcr

alternate pin function values

uint32_t simmask

bit in the SIM register

unsigned long ssi_sysctl

SSI device in sysctl.

unsigned long ssi_base

SSI base address.

unsigned long gpio_sysctl

GPIO device in sysctl.

unsigned long gpio_port

GPIO port.

unsigned long clk

pin used for SCK

unsigned long fss

pin used for FSS

unsigned long rx

pin used for MISO

unsigned long tx

pin used for MOSI

unsigned long mask

Pin mask.

struct spi_conf_t::@74 pins

Pin setting.

NRF_SPI_Type * dev

SPI device used.

uint8_t sclk

CLK pin.

uint8_t mosi

MOSI pin.

uint8_t miso

MISO pin.

SercomSpi * dev

pointer to the used SPI device

gpio.h::gpio_t clk_pin

used CLK pin

sam0_common/include/periph_cpu_common.h::gpio_mux_t miso_mux

alternate function for MISO pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t mosi_mux

alternate function for MOSI pin (mux)

sam0_common/include/periph_cpu_common.h::gpio_mux_t clk_mux

alternate function for CLK pin (mux)

sam0_common/include/periph_cpu_common.h::spi_misopad_t miso_pad

pad to use for MISO line

sam0_common/include/periph_cpu_common.h::spi_mosipad_t mosi_pad

pad to use for MOSI and CLK line

Spi * dev

SPI module to use.

uint8_t id

corresponding ID of that module

gpio.h::gpio_t clk

pin mapped to the CLK line

gpio.h::gpio_t mosi

pin mapped to the MOSI line

gpio.h::gpio_t miso

pin mapped to the MISO line

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

pin MUX setting

SPI_TypeDef * dev

SPI device base register address.

gpio.h::gpio_t sclk_pin

SCLK pin.

stm32_common/include/periph_cpu_common.h::gpio_af_t af

pin alternate function

uint32_t rccmask

bit in the RCC peripheral enable register

uint8_t apbbus

APBx bus the device is connected to.

struct uart_conf_t

UART device configuration.

Structure for UART configuration data.

UART configuration data.

UART module configuration options.

cc2538_uart_t * dev

pointer to the used UART device

UART device base register address.

Pointer to module hardware registers.

gpio.h::gpio_t rx_pin

pin used for RX

RX pin.

Pin used for RX.

gpio.h::gpio_t tx_pin

pin used for TX

TX pin.

Pin used for TX.

gpio.h::gpio_t cts_pin

CTS pin - set to GPIO_UNDEF when not using.

gpio.h::gpio_t rts_pin

RTS pin - set to GPIO_UNDEF when not using.

void * dev

UART, USART or LEUART device used.

Pointer to module hardware registers.

uint32_t loc

location of UART pins

CMU_Clock_TypeDef cmu

the device CMU channel

cc2538.h::IRQn_Type irq

the devices base IRQ channel

USART_TypeDef * dev

USART device used.

UART device base register address.

uint8_t loc

location of USART pins (AF)

uint8_t cmu

the device CMU channel

uint8_t irq

the devices base IRQ channel

uint32_t freq

Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.

gpio.h::gpio_t pin_rx

RX pin, GPIO_UNDEF disables RX.

gpio.h::gpio_t pin_tx

TX pin.

uint32_t pcr_rx

Pin configuration register bits for RX.

uint32_t pcr_tx

Pin configuration register bits for TX.

uint32_t * scgc_addr

Clock enable register, in SIM module.

uint8_t scgc_bit

Clock enable bit, within the register.

kinetis/include/periph_cpu.h::uart_mode_t mode

UART mode: data bits, parity, stop bits.

kinetis/include/periph_cpu.h::uart_type_t type

Hardware module type (KINETIS_UART or KINETIS_LPUART)

SercomUsart * dev

pointer to the used UART device

sam0_common/include/periph_cpu_common.h::gpio_mux_t mux

alternative function for pins

MUX used for pins.

sam0_common/include/periph_cpu_common.h::uart_rxpad_t rx_pad

pad selection for RX line

sam0_common/include/periph_cpu_common.h::uart_txpad_t tx_pad

pad selection for TX line

sam0_common/include/periph_cpu_common.h::uart_flag_t flags

set optional SERCOM flags

uint32_t gclk_src

GCLK source which supplys SERCOM.

Uart * dev

U(S)ART device used.

uint8_t pmc_id

bit in the PMC register of the device

cc2538.h::IRQn_Type irqn

IRQ number for this module.

IRQ channel.

uint32_t rcc_mask

bit in clock enable register

stm32_common/include/periph_cpu_common.h::gpio_af_t rx_af

alternate function for RX pin

stm32_common/include/periph_cpu_common.h::gpio_af_t tx_af

alternate function for TX pin

uint8_t bus

APB bus.

struct clock_config_t

Clock configuration for Kinetis CPUs.

uint32_t clkdiv1

Clock divider bitfield setting.

The value will be written to the SIM_CLKDIV1 hardware register without any transformation. Use the SIM_CLKDIV1_OUTDIVx() macros to ensure the proper bit shift for the chosen divider settings.

See also

CPU reference manual, SIM_CLKDIV1

uint32_t rtc_clc

RTC oscillator Capacitor Load Configuration bits.

The bits will be passed directly to the RTC_CR register without any transformation, i.e. the SC16P bit is (unintuitively) at bit position 10, SC8P is at position 11, and so on (see details in the reference manual). Use the RTC_CR_SCxP_MASK macros to avoid accidentally reversing the bits here.

See also

CPU reference manual, RTC_CR[SCxP]

uint32_t osc32ksel

ERCLK32K 32 kHz reference selection.

The bits will be passed directly to the SIM_SOPT1 register without any transformation, use the SIM_SOPT1_OSC32KSEL() macro to ensure the proper bit shift for the chosen setting.

This signal is the input clock to the RTC module on some CPUs and an input option for the LPTMRx modules. On other CPUs the RTC is clocked directly by the RTC oscillator output without passing through this clock multiplexer.

See also

CPU reference manual, SIM_SOPT1[OSC32KSEL]

unsigned int clock_flags

Flags which will enable various clocking options at init.

See also

kinetis/include/periph_cpu.h::kinetis_clock_flags_t

kinetis/include/periph_cpu.h::kinetis_mcg_mode_t default_mode

MCG mode used after initialization.

See also

kinetis/include/periph_cpu.h::kinetis_mcg_mode_t

kinetis/include/periph_cpu.h::kinetis_mcg_erc_range_t erc_range

ERC range setting.

See also

kinetis/include/periph_cpu.h::kinetis_mcg_erc_range_t

uint8_t osc_clc

OSC0 Capacitor Load Configuration bits.

The bits will be passed directly to the OSC_CR register without any transformation, i.e. the SC16P bit is (unintuitively) the LSB, SC8P is the next bit, and so on (see details in the reference manual). Use the OSC_CR_SCxP_MASK macros to avoid accidentally reversing the bits here.

See also

CPU reference manual, OSC_CR[SCxP]

uint8_t oscsel

MCG external reference oscillator selection.

The bits will be passed directly to the MCG_C7 register without any transformation, use the MCG_C7_OSCSEL() macro to ensure the proper bit shift for the chosen setting.

See also

CPU reference manual, MCG_C7[OSCSEL]

uint8_t fcrdiv

Fast internal reference clock divider.

The bits will be passed directly to the MCG_SC register without any transformation, use the MCG_SC_FCRDIV() macro to ensure the proper bit shift for the chosen setting.

See also

CPU reference manual, MCG_SC[FCRDIV]

uint8_t fll_frdiv

FLL ERC divider setting.

The bits will be passed directly to the MCG_C1 register without any transformation, use the MCG_C1_FRDIV() macro to ensure the proper bit shift for the chosen setting.

See also

CPU reference manual, MCG_C1[FRDIV]

kinetis/include/periph_cpu.h::kinetis_mcg_fll_t fll_factor_fei

FLL multiplier when running in FEI mode.

See also

kinetis/include/periph_cpu.h::kinetis_mcg_fll_t

See also

CPU reference manual, MCG_C4[DMX32, DRST_DRS]

kinetis/include/periph_cpu.h::kinetis_mcg_fll_t fll_factor_fee

FLL multiplier when running in FEE mode.

See also

kinetis/include/periph_cpu.h::kinetis_mcg_fll_t

See also

CPU reference manual, MCG_C4[DMX32, DRST_DRS]

uint8_t pll_prdiv

PLL ERC divider setting.

The bits will be passed directly to the MCG_C5 register without any transformation, use the MCG_C5_PRDIV0() macro to ensure the proper bit shift for the chosen setting.

See also

CPU reference manual, MCG_C5[PRDIV0]

uint8_t pll_vdiv

PLL VCO divider setting.

The bits will be passed directly to the MCG_C6 register without any transformation, use the MCG_C6_VDIV0() macro to ensure the proper bit shift for the chosen setting.

See also

CPU reference manual, MCG_C6[VDIV0]