encx24j600_defines.h¶
Register definitions for the ENCX24J600 Ethernet device.
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ENC_RCR¶ 1
0x00 /* read control register */
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ENC_WCR¶ 1
0x04 /* write control register */
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ENC_RCRU¶ 1
0x20 /* read control register unbanked */
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ENC_WCRU¶ 1
0x22 /* write control register unbanked */
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ENC_BFSU¶ 1
0x24 /* set bits unbanked */
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ENC_BFCU¶ 1
0x26 /* clear bits unbanked */
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ENC_RGPDATA¶ 1
0x28 /* Read EGPDATA */
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ENC_WGPDATA¶ 1
0x2a /* Write EGPDATA */
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ENC_RRXDATA¶ 1
0x2c /* Read ERXDATA */
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ENC_WRXDATA¶ 1
0x2e /* Write ERXDATA */
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ENC_RUDADATA¶ 1
0x30 /* Read EUDADATA */
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ENC_WUDADATA¶ 1
0x32 /* Write EUDADATA */
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ENC_BFS¶ 1
0x80 /* Bit Field Set */
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ENC_BFC¶ 1
0xa0 /* Bit Field Clear */
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ENC_SETETHRST¶ 1
0xca /* System Reset */
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ENC_SETPKTDEC¶ 1
0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
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ENC_ENABLERX¶ 1
0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
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ENC_DISABLERX¶ 1
0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
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ENC_SETEIE¶ 1
0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
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ENC_CLREIE¶ 1
0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
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ENC_B0SEL¶ 1
0xc0 /* select bank 0 */
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ENC_B1SEL¶ 1
0xc2 /* select bank 0 */
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ENC_B2SEL¶ 1
0xc4 /* select bank 0 */
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ENC_B3SEL¶ 1
0xc6 /* select bank 0 */
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ENC_RBSEL¶ 1
0xc8 /* Read Bank Select */
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ENC_SETTXRTS¶ 1
0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
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ENC_ETXST¶ 1
0x00
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ENC_ETXLEN¶ 1
0x02
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ENC_ERXST¶ 1
0x04
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ENC_ERXTAIL¶ 1
0x06
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ENC_ERXHEAD¶ 1
0x08
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ENC_ETXSTAT¶ 1
0x12
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ENC_ETXWIRE¶ 1
0x14
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ENC_EUDAST¶ 1
0x16
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ENC_ESTAT¶ 1
0x1a
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ENC_EIR¶ 1
0x1c /* Interrupt Flag Register */
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ENC_ECON1¶ 1
0x1e
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ENC_ERXFCON¶ 1
0x34 /* Receive filter control register */
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ENC_MACON2¶ 1
0x42
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ENC_MAMXFL¶ 1
0x4a /* MAC maximum frame length */
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ENC_MAADR3¶ 1
0x60 /* MAC address byte 5&6 */
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ENC_MAADR2¶ 1
0x62 /* MAC address byte 3&4 */
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ENC_MAADR1¶ 1
0x64 /* MAC address byte 1&2 */
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ENC_MIWR¶ 1
0x66
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ENC_MIREGADR¶ 1
0x54
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ENC_ECON2¶ 1
0x6e
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ENC_EIE¶ 1
0x72 /* Interrupt Enable Register */
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ENC_EGPRDPT¶ 1
0x86 /* General Purpose SRAM read pointer */
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ENC_EGPWRPT¶ 1
0x88 /* General Purpose SRAM write pointer */
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ENC_ERXRDPT¶ 1
0x8a /* RX buffer read pointer */
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ENC_ERXWRPT¶ 1
0x8c /* RX buffer write pointer */
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ENC_PHCON1¶ 1
0x00
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ENC_PHSTAT1¶ 1
0x01
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ENC_PHANA¶ 1
0x04
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ENC_PHANLPA¶ 1
0x05
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ENC_PHANE¶ 1
0x06
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ENC_PHCON2¶ 1
0x11
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ENC_PHSTAT2¶ 1
0x1b
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ENC_PHSTAT3¶ 1
0x1f
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ENC_PHYLNK¶ 1
(1<<8)
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ENC_CLKRDY¶ 1
(1<<12)
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ENC_RXEN¶ 1
(1<<0)
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ENC_TXRTS¶ 1
(1<<1)
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ENC_DMANOCS¶ 1
(1<<2)
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ENC_DMACSSD¶ 1
(1<<3)
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ENC_DMACPY¶ 1
(1<<4)
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ENC_DMAST¶ 1
(1<<5)
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ENC_FCOP0¶ 1
(1<<6)
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ENC_FCOP1¶ 1
(1<<7)
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ENC_PKTDEC¶ 1
(1<<8)
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ENC_AESOP0¶ 1
(1<<9)
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ENC_AESOP1¶ 1
(1<<10)
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ENC_AESST¶ 1
(1<<11)
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ENC_HASHLST¶ 1
(1<<12)
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ENC_HASHOP¶ 1
(1<<13)
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ENC_HASHEN¶ 1
(1<<14)
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ENC_MODEXST¶ 1
(1<<15)
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ENC_ETHRST¶ 1
(1<<4)
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ENC_AUTOFC¶ 1
(1<<7) /* automatic flow control enable bit */
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ENC_PCFULIE¶ 1
(1<<0)
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ENC_RXABTIE¶ 1
(1<<1)
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ENC_TXABTIE¶ 1
(1<<2)
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ENC_TXIE¶ 1
(1<<3)
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ENC_DMAIE¶ 1
(1<<5)
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ENC_PKTIE¶ 1
(1<<6)
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ENC_LINKIE¶ 1
(1<<11)
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ENC_AESIE¶ 1
(1<<12)
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ENC_HASHIE¶ 1
(1<<13)
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ENC_MODEXIE¶ 1
(1<<14)
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ENC_INTIE¶ 1
(1<<15)
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ENC_PCFULIF¶ 1
(1<<0)
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ENC_RXABTIF¶ 1
(1<<1)
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ENC_TXABTIF¶ 1
(1<<2)
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ENC_TXIF¶ 1
(1<<3)
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ENC_DMAIF¶ 1
(1<<5)
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ENC_PKTIF¶ 1
(1<<6)
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ENC_LINKIF¶ 1
(1<<11)
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ENC_AESIF¶ 1
(1<<12)
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ENC_HASHIF¶ 1
(1<<13)
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ENC_MODEXIF¶ 1
(1<<14)
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ENC_CRYPTEN¶ 1
(1<<15)
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ENC_MCEN¶ 1
(1<<1)