atmega_common/include/periph_cpu_common.h

CPU specific definitions for internal peripheral handling.

GPIO_UNDEF

Definition of a fitting UNDEF value.

(0xff)

GPIO_PIN( x, y)

Define a CPU specific GPIO pin generator macro.

((x << 4) | y)

HAVE_GPIO_FLANK_T

Override the GPIO flanks.

This device has an additional mode in which the interrupt is triggered when the pin is low.

Enumeration order is important, do not modify.

enum gpio_flank_t

GPIO_NONE = 0

GPIO_LOW

emit interrupt when pin low

GPIO_HIGH = 5

emit interrupt on low level

GPIO_FALLING

emit interrupt on falling flank

GPIO_RISING

emit interrupt on rising flank

GPIO_BOTH

emit interrupt on both flanks

PERIPH_SPI_NEEDS_INIT_CS

Use some common SPI functions.

PERIPH_SPI_NEEDS_TRANSFER_BYTE

PERIPH_SPI_NEEDS_TRANSFER_REG

PERIPH_SPI_NEEDS_TRANSFER_REGS

HAVE_SPI_MODE_T

Override the SPI mode values.

As the mode is set in bit 3 and 2 of the configuration register, we put the correct configuration there

enum spi_mode_t

SPI_MODE_0 = SPI_MODE_SEL(0, 0)

mode 0

SPI_MODE_1 = SPI_MODE_SEL(0, 1)

mode 1

SPI_MODE_2 = SPI_MODE_SEL(1, 0)

mode 2

SPI_MODE_3 = SPI_MODE_SEL(1, 1)

mode 3

HAVE_SPI_CLK_T

Override SPI speed values.

We assume a master clock speed of 16MHz here.

enum spi_clk_t

SPI_CLK_4MHZ = 4000000

drive the SPI bus with 4MHz

SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1)

16/128 -> 125KHz

SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0)

16/32 -> 500KHz

SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1)

16/16 -> 1MHz

SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0)

16/4 -> 4MHz

SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)

16/2 -> 8MHz

enum timer_div_t

TIMER_DIV1_8_64_128_1024 = 0x549

1/{1,8,64,128,1024}

TIMER_DIV1_8_32_64_128_256_1024 = 0x5E9

1/{1,8,32,64,128,256,1024}

SPI_MODE_SEL( pol, pha)

SPI mode select macro.

((pol << 3) | (pha << 2))

The polarity is determined by bit 3 in the configuration register, the phase by bit 2.

SPI_CLK_SEL( s2x, pr1, pr0)

SPI speed selection macro.

((s2x << 2) | (pr1 << 1) | pr0)

We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR prescaler bits, while bit2 holds the SPI2X bit.

struct pwm_conf_t

PWM configuration.

PWM device configuration data structure.

PWM configuration options.

PWM device configuration.

Each device supports up to 4 channels. If you want to use less than 4 channels, just set the unused pins to GPIO_UNDEF.

Note

define unused pins only from right to left, so the defined channels always start with channel 0 to x and the undefined ones are from x+1 to PWM_CHANNELS.

mini_timer_t * dev

Timer used.

gpio.h::gpio_t pin_ch()

Output Pins.

atmega_common/include/periph_cpu_common.h::timer_div_t div

Timer divider mask.

TIMER_TypeDef * dev

TIMER device used.

CMU_Clock_TypeDef cmu

the device CMU channel

cc2538.h::IRQn_Type irq

the devices base IRQ channel

uint8_t channels

the number of available channels

const pwm_chan_conf_t * channel

pointer to first channel config

NRF_PWM_Type * dev

PWM device descriptor.

uint32_t pin()

PWM out pins.

Tcc * dev

TCC device to use.

pwm_conf_chan_t chan()

channel configuration

TIM_TypeDef * dev

Timer used.

uint32_t rcc_mask

bit in clock enable register

pwm_chan_t chan()

channel mapping, set to {GPIO_UNDEF, 0} if not used

stm32_common/include/periph_cpu_common.h::gpio_af_t af

alternate function used

uint8_t bus

APB bus.