LIS3DH accelerometer

Device driver for the LIS3DH accelerometer.

This driver provides [S]ensor [A]ctuator [U]ber [L]ayer capabilities.

LIS3DH_REG_STATUS_AUX
1
(0x07)
LIS3DH_REG_OUT_AUX_ADC1_L
1
(0x08)
LIS3DH_REG_OUT_AUX_ADC1_H
1
(0x09)
LIS3DH_REG_OUT_AUX_ADC2_L
1
(0x0A)
LIS3DH_REG_OUT_AUX_ADC2_H
1
(0x0B)
LIS3DH_REG_OUT_AUX_ADC3_L
1
(0x0C)
LIS3DH_REG_OUT_AUX_ADC3_H
1
(0x0D)
LIS3DH_REG_INT_COUNTER_REG
1
(0x0E)
LIS3DH_REG_WHO_AM_I
1
(0x0F)
LIS3DH_REG_TEMP_CFG_REG
1
(0x1F)
LIS3DH_REG_CTRL_REG1
1
(0x20)
LIS3DH_REG_CTRL_REG2
1
(0x21)
LIS3DH_REG_CTRL_REG3
1
(0x22)
LIS3DH_REG_CTRL_REG4
1
(0x23)
LIS3DH_REG_CTRL_REG5
1
(0x24)
LIS3DH_REG_CTRL_REG6
1
(0x25)
LIS3DH_REG_REFERENCE
1
(0x26)
LIS3DH_REG_STATUS_REG
1
(0x27)
LIS3DH_REG_OUT_X_L
1
(0x28)
LIS3DH_REG_OUT_X_H
1
(0x29)
LIS3DH_REG_OUT_Y_L
1
(0x2A)
LIS3DH_REG_OUT_Y_H
1
(0x2B)
LIS3DH_REG_OUT_Z_L
1
(0x2C)
LIS3DH_REG_OUT_Z_H
1
(0x2D)
LIS3DH_REG_FIFO_CTRL_REG
1
(0x2E)
LIS3DH_REG_FIFO_SRC_REG
1
(0x2F)
LIS3DH_REG_INT1_CFG
1
(0x30)
LIS3DH_REG_INT1_SOURCE
1
(0x31)
LIS3DH_REG_INT1_THS
1
(0x32)
LIS3DH_REG_INT1_DURATION
1
(0x33)
LIS3DH_REG_CLICK_CFG
1
(0x38)
LIS3DH_REG_CLICK_SRC
1
(0x39)
LIS3DH_REG_CLICK_THS
1
(0x3A)
LIS3DH_REG_TIME_LIMIT
1
(0x3B)
LIS3DH_REG_TIME_LATENCY
1
(0x3C)
LIS3DH_REG_TIME_WINDOW
1
(0x3D)
LIS3DH_TEMP_CFG_REG_ADC_PD_MASK

ADC enable. 

1
(1 << 7)

Default value: 0

0: ADC disabled; 1: ADC enabled

LIS3DH_TEMP_CFG_REG_TEMP_EN_MASK

Temperature sensor (T) enable. 

1
(1 << 6)

Default value: 0

0: T disabled; 1: T enabled

LIS3DH_CTRL_REG1_ODR_SHIFT

ODR global shift. 

1
(4)
LIS3DH_CTRL_REG1_ODR3_MASK

ODR fourth bit mask. 

1
(1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 3))
LIS3DH_CTRL_REG1_ODR2_MASK

ODR third bit mask. 

1
(1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 2))
LIS3DH_CTRL_REG1_ODR1_MASK

ODR second bit mask. 

1
(1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 1))
LIS3DH_CTRL_REG1_ODR0_MASK

ODR first bit mask. 

1
(1 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_CTRL_REG1_ODR_MASK

Output data rate (ODR) selection bitfield. 

1
2
3
4
(LIS3DH_CTRL_REG1_ODR3_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR2_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR1_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR0_MASK)

Default value: 0000

0000: Power down; Others: Refer to data sheet

See also

LIS3DH data sheet Table 25, “Data rate configuration”

LIS3DH_CTRL_REG1_LPEN_MASK

Low power mode enable. 

1
(1 << 3)

Default value: 0

0. normal mode

  1. low power mode

LIS3DH_CTRL_REG1_ZEN_SHIFT

Z enable bit offset. 

1
(2)
LIS3DH_CTRL_REG1_ZEN_MASK

Z axis enable. 

1
(1 << LIS3DH_CTRL_REG1_ZEN_SHIFT)

Default value: 1

0. Z axis disabled

  1. Z axis enabled

LIS3DH_CTRL_REG1_YEN_SHIFT

Y enable bit offset. 

1
(1)
LIS3DH_CTRL_REG1_YEN_MASK

Y axis enable. 

1
(1 << LIS3DH_CTRL_REG1_YEN_SHIFT)

Default value: 1

0. Y axis disabled

  1. Y axis enabled

LIS3DH_CTRL_REG1_XEN_SHIFT

X enable bit offset. 

1
(0)
LIS3DH_CTRL_REG1_XEN_MASK

X axis enable. 

1
(1 << LIS3DH_CTRL_REG1_XEN_SHIFT)

Default value: 1

0. X axis disabled

  1. X axis enabled

LIS3DH_CTRL_REG1_XYZEN_SHIFT

XYZ enable bitfield offset. 

1
(0)
LIS3DH_CTRL_REG1_XYZEN_MASK

X, Y, Z enable bitfield mask. 

1
2
(LIS3DH_CTRL_REG1_XEN_MASK | \
                                                  LIS3DH_CTRL_REG1_YEN_MASK | LIS3DH_CTRL_REG1_ZEN_MASK)
LIS3DH_AXES_X

enable X axis (Use when calling lis3dh.h::lis3dh_set_axes()) 

1
(LIS3DH_CTRL_REG1_XEN_MASK)
LIS3DH_AXES_Y

enable Y axis (Use when calling lis3dh.h::lis3dh_set_axes()) 

1
(LIS3DH_CTRL_REG1_YEN_MASK)
LIS3DH_AXES_Z

enable Z axis (Use when calling lis3dh.h::lis3dh_set_axes()) 

1
(LIS3DH_CTRL_REG1_ZEN_MASK)
LIS3DH_CTRL_REG2_HPM1_MASK

High pass filter mode selection second bit. 

1
(1 << 7)

Default value: 0

See also

Refer to Table 29, “High pass filter mode configuration”

LIS3DH_CTRL_REG2_HPM0_MASK

High pass filter mode selection first bit. 

1
(1 << 6)

Default value: 0

See also

Refer to Table 29, “High pass filter mode configuration”

LIS3DH_CTRL_REG2_HPCF2_MASK

High pass filter cut off frequency selection second bit. 

1
(1 << 5)
LIS3DH_CTRL_REG2_HPCF1_MASK

High pass filter cut off frequency selection second bit. 

1
(1 << 4)
LIS3DH_CTRL_REG2_FDS_MASK

Filtered data selection. 

1
(1 << 3)

Default value: 0

0. internal filter bypassed

  1. data from internal filter sent to output register and FIFO

LIS3DH_CTRL_REG2_HPCLICK_MASK

High pass filter enabled for CLICK function. 

1
(1 << 2)

0. filter bypassed

  1. filter enabled

LIS3DH_CTRL_REG2_HPIS2_MASK

High pass filter enabled for AOI function on interrupt 2, second bit. 

1
(1 << 1)

0. filter bypassed

  1. filter enabled

LIS3DH_CTRL_REG2_HPIS1_MASK

High pass filter enabled for AOI function on interrupt 2, first bit. 

1
(1 << 0)

0. filter bypassed

  1. filter enabled

LIS3DH_CTRL_REG3_I1_CLICK_MASK

CLICK interrupt on INT1. 

1
(1 << 7)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_AOI1_MASK

AOI1 interrupt on INT1. 

1
(1 << 6)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_AOI2_MASK

AOI2 interrupt on INT1. 

1
(1 << 5)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_DRDY1_MASK

DRDY1 interrupt on INT1. 

1
(1 << 4)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_DRDY2_MASK

DRDY2 interrupt on INT1. 

1
(1 << 3)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_WTM_MASK

FIFO Watermark interrupt on INT1. 

1
(1 << 2)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG3_I1_OVERRUN_MASK

FIFO Overrun interrupt on INT1. 

1
(1 << 1)

Default value 0.

0. Disable

  1. Enable

LIS3DH_CTRL_REG4_BDU_MASK

Block data update (BDU) bit mask. 

1
(1 << 7)

Default value of BDU: 0

0. continuous update

  1. output registers not updated until MSB and LSB reading

LIS3DH_CTRL_REG4_BDU_ENABLE

Block data update (BDU) enable. 

1
(LIS3DH_CTRL_REG4_BDU_MASK)
LIS3DH_CTRL_REG4_BDU_DISABLE

Block data update (BDU) disable. 

1
(0)
LIS3DH_CTRL_REG4_BLE_MASK

Big/little endian bit mask. 

1
(1 << 6)

Default value of BLE: 0.

0. Data LSB @ lower address

  1. Data MSB @ lower address

LIS3DH_CTRL_REG4_BLE_LITTLE_ENDIAN

Big/little endian little endian mode. 

1
(0)
LIS3DH_CTRL_REG4_BLE_BIG_ENDIAN

Big/little endian big endian mode. 

1
(LIS3DH_CTRL_REG4_BLE_MASK)
LIS3DH_CTRL_REG4_FS1_MASK

Full scale selection mask second bit. 

1
(1 << 5)
LIS3DH_CTRL_REG4_FS0_MASK

Full scale selection mask first bit. 

1
(1 << 4)
LIS3DH_CTRL_REG4_FS_MASK

Full scale selection mask. 

1
2
(LIS3DH_CTRL_REG4_FS1_MASK | \
                                                  LIS3DH_CTRL_REG4_FS0_MASK)
LIS3DH_CTRL_REG4_SCALE_2G

Scale register value: +/- 2G. 

1
(0)
LIS3DH_CTRL_REG4_SCALE_4G

Scale register value: +/- 4G. 

1
(LIS3DH_CTRL_REG4_FS0_MASK)
LIS3DH_CTRL_REG4_SCALE_8G

Scale register value: +/- 8G. 

1
(LIS3DH_CTRL_REG4_FS1_MASK)
LIS3DH_CTRL_REG4_SCALE_16G

Scale: +/- 16G. 

1
(LIS3DH_CTRL_REG4_FS1_MASK | LIS3DH_CTRL_REG4_FS0_MASK)
LIS3DH_CTRL_REG4_HR_MASK

High resolution output mode. 

1
(1 << 3)

Default value: 0

0. High resolution disable

  1. High resolution enable

LIS3DH_CTRL_REG4_ST1_MASK

Self test enable second bit mask. 

1
(1 << 2)

Default value of self test: 00

  • 00: Self test disabled
  • Other: See Table 34

See also

Table 34

LIS3DH_CTRL_REG4_ST0_MASK

Self test enable first bit mask. 

1
(1 << 1)
LIS3DH_CTRL_REG4_SIM_MASK

SPI serial interface mode selection. 

1
(1 << 0)

Default value: 0

0. 4-wire interface

  1. 3-wire interface

LIS3DH_CTRL_REG5_REBOOT_MASK

Reboot memory content. 

1
(1 << 7)

Default value: 0

0. normal mode

  1. reboot memory content

LIS3DH_CTRL_REG5_FIFO_EN_MASK

FIFO enable. 

1
(1 << 6)

Default value: 0

0. FIFO disable

  1. FIFO enable

LIS3DH_CTRL_REG5_LIR_I1_MASK

Latch interrupt request on INT1. 

1
(1 << 3)

Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC itself.

Default value: 0

0. interrupt request not latched

  1. interrupt request latched

LIS3DH_CTRL_REG5_D4D_I1_MASK

4D enable 

1
(1 << 2)

4D detection is enabled on INT1 when 6D bit on INT1_CFG is set to 1.

LIS3DH_STATUS_REG_ZYXOR_MASK

X, Y or Z axis data overrun. 

1
(1 << 7)

Default value: 0

0. no overrun has occurred

  1. a new set of data has overwritten the previous ones

LIS3DH_STATUS_REG_ZOR_MASK

Z axis data overrun. 

1
(1 << 6)

Default value: 0

0. no overrun has occurred

  1. a new data for the Z-axis has overwritten the previous one

LIS3DH_STATUS_REG_YOR_MASK

Y axis data overrun. 

1
(1 << 5)

Default value: 0

0. no overrun has occurred

  1. a new data for the Y-axis has overwritten the previous one

LIS3DH_STATUS_REG_XOR_MASK

X axis data overrun. 

1
(1 << 4)

Default value: 0

0. no overrun has occurred

  1. a new data for the X-axis has overwritten the previous one

LIS3DH_STATUS_REG_ZYXDA_MASK

X, Y or Z axis new data available. 

1
(1 << 3)

Default value: 0

0. a new set of data is not yet available

  1. a new set of data is available

LIS3DH_STATUS_REG_ZDA_MASK

Z axis new data available. 

1
(1 << 2)

Default value: 0

0. a new data for the Z-axis is not yet available

  1. a new data for the Z-axis is available

LIS3DH_STATUS_REG_YDA_MASK

Y axis new data available. 

1
(1 << 1)

Default value: 0

0. a new data for the Y-axis is not yet available

  1. a new data for the Y-axis is available

LIS3DH_STATUS_REG_XDA_MASK

X axis new data available. 

1
(1 << 0)

Default value: 0

0. a new data for the X-axis is not yet available

  1. a new data for the X-axis is available

LIS3DH_FIFO_CTRL_REG_FM_SHIFT
1
(6)
LIS3DH_FIFO_CTRL_REG_FM1_MASK
1
(1 << 7)
LIS3DH_FIFO_CTRL_REG_FM0_MASK
1
(1 << 6)
LIS3DH_FIFO_CTRL_REG_FM_MASK
1
2
(LIS3DH_FIFO_CTRL_REG_FM1_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FM0_MASK)
LIS3DH_FIFO_CTRL_REG_TR_MASK
1
(1 << 5)
LIS3DH_FIFO_CTRL_REG_FTH4_MASK
1
(1 << 4)
LIS3DH_FIFO_CTRL_REG_FTH3_MASK
1
(1 << 3)
LIS3DH_FIFO_CTRL_REG_FTH2_MASK
1
(1 << 2)
LIS3DH_FIFO_CTRL_REG_FTH1_MASK
1
(1 << 1)
LIS3DH_FIFO_CTRL_REG_FTH0_MASK
1
(1 << 0)
LIS3DH_FIFO_CTRL_REG_FTH_SHIFT
1
(0)
LIS3DH_FIFO_CTRL_REG_FTH_MASK
1
2
3
4
5
(LIS3DH_FIFO_CTRL_REG_FTH0_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH1_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH2_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH3_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH4_MASK)
LIS3DH_FIFO_SRC_REG_WTM_MASK
1
(1 << 7)
LIS3DH_FIFO_SRC_REG_OVRN_FIFO_MASK
1
(1 << 6)
LIS3DH_FIFO_SRC_REG_EMPTY_MASK
1
(1 << 5)
LIS3DH_FIFO_SRC_REG_FSS4_MASK
1
(1 << 4)
LIS3DH_FIFO_SRC_REG_FSS3_MASK
1
(1 << 3)
LIS3DH_FIFO_SRC_REG_FSS2_MASK
1
(1 << 2)
LIS3DH_FIFO_SRC_REG_FSS1_MASK
1
(1 << 1)
LIS3DH_FIFO_SRC_REG_FSS0_MASK
1
(1 << 0)
LIS3DH_FIFO_SRC_REG_FSS_SHIFT
1
(0)
LIS3DH_FIFO_SRC_REG_FSS_MASK
1
2
3
4
5
(LIS3DH_FIFO_SRC_REG_FSS0_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS1_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS2_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS3_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS4_MASK)
LIS3DH_SPI_WRITE_MASK

Write to register. 

1
(0 << 7)
LIS3DH_SPI_READ_MASK

The READ bit must be set when reading. 

1
(1 << 7)
LIS3DH_SPI_MULTI_MASK

Multi byte transfers must assert this bit when writing the address. 

1
(1 << 6)
LIS3DH_SPI_SINGLE_MASK

Opposite of LIS3DH_SPI_MULTI_MASK. 

1
(0 << 6)
LIS3DH_SPI_ADDRESS_MASK

Mask of the address bits in the address byte during transfers. 

1
(0x3F)
LIS3DH_FIFO_MODE_BYPASS

FIFO mode: Bypass. 

1
(0x00 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
LIS3DH_FIFO_MODE_FIFO

FIFO mode: FIFO. 

1
(0x01 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
LIS3DH_FIFO_MODE_STREAM

FIFO mode: Stream. 

1
(0x02 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
LIS3DH_FIFO_MODE_STREAM_TO_FIFO

FIFO mode: Stream to FIFO. 

1
(0x03 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
LIS3DH_ODR_POWERDOWN

Powerdown mode. 

1
(0x00 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_1Hz

1Hz mode 

1
(0x01 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_10Hz

10Hz mode 

1
(0x02 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_25Hz

25Hz mode 

1
(0x03 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_50Hz

50Hz mode 

1
(0x04 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_100Hz

100Hz mode 

1
(0x05 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_200Hz

200Hz mode 

1
(0x06 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_400Hz

400Hz mode 

1
(0x07 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_LP1600Hz

Low power 1600Hz mode. 

1
(0x08 << LIS3DH_CTRL_REG1_ODR_SHIFT)
LIS3DH_ODR_NP1250Hz

Normal mode 1250 Hz. 

1
(0x09 << LIS3DH_CTRL_REG1_ODR_SHIFT)

Note

Normal mode 1250 Hz and Low power mode 5000 Hz share the same setting

LIS3DH_ODR_LP5000HZ

Low power mode 5000 Hz. 

1
(0x09 << LIS3DH_CTRL_REG1_ODR_SHIFT)

Note

Normal mode 1250 Hz and Low power mode 5000 Hz share the same setting

int lis3dh_init(lis3dh_t * dev, const lis3dh_params_t * params)

Initialize a LIS3DH sensor instance.

Parameters

dev:Device descriptor of sensor to initialize
params:Configuration parameters

Return values

  • 0 on success
  • -1 on error
int lis3dh_read_xyz(const lis3dh_t * dev, lis3dh_data_t * acc_data)

Read 3D acceleration data from the accelerometer.

Parameters

dev:Device descriptor of sensor
acc_data:Accelerometer data output buffer

Return values

  • 0 on success
  • -1 on error
int lis3dh_read_aux_adc1(const lis3dh_t * dev, int16_t * out)

Read auxiliary ADC channel 1 data from the accelerometer.

Parameters

dev:Device descriptor of sensor
out:The value of ADC1 (OUT_1_{L,H}) will be written to this buffer

Return values

  • 0 on success
  • -1 on error
int lis3dh_read_aux_adc2(const lis3dh_t * dev, int16_t * out)

Read auxiliary ADC channel 2 data from the accelerometer.

Parameters

dev:Device descriptor of sensor
out:The value of ADC2 (OUT_2_{L,H}) will be written to this buffer

Return values

  • 0 on success
  • -1 on error
int lis3dh_read_aux_adc3(const lis3dh_t * dev, int16_t * out)

Read auxiliary ADC channel 3 data from the accelerometer.

Parameters

dev:Device descriptor of sensor
out:The value of ADC3 (OUT_3_{L,H}) will be written to this buffer

Note

The internal temperature sensor is connected to the third channel on the auxiliary ADC when the TEMP_EN bit of TEMP_CFG_REG is set.

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_aux_adc(const lis3dh_t * dev, const uint8_t enable, const uint8_t temperature)

Turn on/off power to the auxiliary ADC in LIS3DH.

Parameters

dev:Device descriptor of sensor
enable:Power state of the auxiliary ADC
temperature:If not zero, switch the ADC mux so that a temperature reading is available on OUT_3_L, OUT_3_H.

Note

This ADC is only used for the temperature reading and the external ADC pins. The accelerometer ADC is turned on by lis3dh.h::lis3dh_set_odr().

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_axes(const lis3dh_t * dev, const uint8_t axes)

Enable/disable accelerometer axes.

Parameters

dev:Device descriptor of sensor
axes:An OR-ed combination of LIS3DH_AXES_X, LIS3DH_AXES_Y, LIS3DH_AXES_Z.

Note

The macro LIS3DH_AXES_XYZ is a convenience shortcut to enable all axes.

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_fifo(const lis3dh_t * dev, const uint8_t mode, const uint8_t watermark)

Enable/disable the FIFO.

Parameters

dev:Device descriptor of sensor
mode:FIFO mode, see data sheet for details.
watermark:Watermark level for FIFO level interrupts

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_odr(const lis3dh_t * dev, const uint8_t odr)

Set the output data rate of the sensor.

Parameters

dev:Device descriptor of sensor
odr:Chosen output data rate.

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_scale(lis3dh_t * dev, const uint8_t scale)

Set the full scale range of the sensor.

Valid values for scale are 2, 4, 8, 16 and represents the full range of the sensor.

Parameters

dev:Device descriptor of sensor
scale:The chosen sensitivity scale.

Return values

  • 0 on success
  • -1 on error
int lis3dh_set_int1(const lis3dh_t * dev, const uint8_t mode)

Set INT1 pin function.

Set the bits of CTRL_REG3 for choosing sources for the INT1 pin.

Parameters

dev:Device descriptor of sensor
mode:CTRL_REG3 value, see data sheet for details.

Return values

  • 0 on success
  • -1 on error
int lis3dh_get_fifo_level(const lis3dh_t * dev)

Get the current number of elements in the FIFO.

Parameters

dev:Device descriptor of sensor

Return values

  • number of elements in device FIFO on success
  • -1 on error
LIS3DH_WHO_AM_I_RESPONSE

Identifier register value. 

1
(0x33)

The WHO_AM_I register should contain this value in order to correctly identify the chip.

LIS3DH_AXES_XYZ

Convenience macro for enabling all axes. 

1
(LIS3DH_CTRL_REG1_XYZEN_MASK)
LIS3DH_ADC_DATA_SIZE

Length of scalar measurement data in bytes. 

1
(2U)
struct lis3dh_params_t

Configuration parameters for LIS3DH devices.

spi.h::spi_t spi

SPI device the sensor is connected to.

atmega_common/include/periph_cpu_common.h::spi_clk_t clk

designated clock speed of the SPI bus

gpio.h::gpio_t cs

Chip select pin.

gpio.h::gpio_t int1

INT1 pin.

gpio.h::gpio_t int2

INT2 (DRDY) pin.

uint8_t scale

Default sensor scale: 2, 4, 8, or 16 (G)

uint8_t odr

Default sensor ODR setting: LIS3DH_ODR_xxxHz.

struct lis3dh_t

Device descriptor for LIS3DH sensors.

lis3dh_params_t params

Device initialization parameters.

uint16_t scale

Internal sensor scale.

struct lis3dh_data_t

Result vector for accelerometer measurement.

int16_t acc_x

Acceleration in the X direction in milli-G.

int16_t acc_y

Acceleration in the Y direction in milli-G.

int16_t acc_z

Acceleration in the Z direction in milli-G.