TI CC26x0 definitions

Texas Instruments CC26x0 specific defines.

UART_DR_DATA_mask

UART register values.

1
0xFF
UART_DR_FE
1
0x100
UART_DR_PE
1
0x200
UART_DR_BE
1
0x400
UART_DR_OE
1
0x800
UART_ECR_FE
1
0x1
UART_ECR_PE
1
0x2
UART_ECR_BE
1
0x4
UART_ECR_OE
1
0x8
UART_FR_CTS
1
0x1
UART_FR_BUSY
1
0x4
UART_FR_RXFE
1
0x10
UART_FR_TXFF
1
0x20
UART_FR_RXFF
1
0x40
UART_FR_TXFE
1
0x80
UART_LCRH_PEN
1
0x1
UART_LCRH_EPS
1
0x2
UART_LCRH_RXFE
1
0x4
UART_LCRH_STP2
1
0x8
UART_LCRH_FEN
1
0x10
UART_LCRH_WLEN_mask
1
0x60
UART_LCRH_WLEN_5
1
0x0
UART_LCRH_WLEN_6
1
0x20
UART_LCRH_WLEN_7
1
0x40
UART_LCRH_WLEN_8
1
0x60
UART_LCRH_SPS
1
0x80
UART_CTL_UARTEN
1
0x1
UART_CTL_LBE
1
0x80
UART_CTL_TXE
1
0x100
UART_CTL_RXE
1
0x200
UART_CTL_RTS
1
0x800
UART_CTL_RTSEN
1
0x4000
UART_CTL_CTSEN
1
0x8000
UART_MIS_CTSMMIS
1
0x1
UART_MIS_RXMIS
1
0x10
UART_MIS_TXMIS
1
0x20
UART_MIS_RTMIS
1
0x40
UART_MIS_FEMIS
1
0x80
UART_MIS_PEMIS
1
0x100
UART_MIS_BEMIS
1
0x200
UART_MIS_OEMIS
1
0x400
UART_IMSC_CTSMIM
1
0x2
UART_IMSC_RXIM
1
0x10
UART_IMSC_TXIM
1
0x20
UART_IMSC_RTIM
1
0x40
UART_IMSC_FEIM
1
0x80
UART_IMSC_PEIM
1
0x100
UART_IMSC_BEIM
1
0x200
UART_IMSC_OEIM
1
0x400
UART_IFLS_TXSEL_1_8
1
0x0
UART_IFLS_TXSEL_2_8
1
0x1
UART_IFLS_TXSEL_4_8
1
0x2
UART_IFLS_TXSEL_6_8
1
0x3
UART_IFLS_TXSEL_7_8
1
0x4
UART_IFLS_RXSEL_1_8
1
0x0
UART_IFLS_RXSEL_2_8
1
0x8
UART_IFLS_RXSEL_4_8
1
0x10
UART_IFLS_RXSEL_6_8
1
0x18
UART_IFLS_RXSEL_7_8
1
0x20
UART_BASE

UART base address.

1
(0x40001000)
UART

UART register bank.

1
((uart_regs_t *) (UART_BASE))
struct uart_regs_t

UART component registers.

reg32_t DR

data

reg32_t RSR

status

reg32_t ECR

error clear

union uart_regs_t::@65 @66
reg32_t __reserved1()

meh

reg32_t FR

flag

reg32_t __reserved2()

meh

reg32_t IBRD

integer baud-rate divisor

reg32_t FBRD

fractional baud-rate divisor

reg32_t LCRH

line control

reg32_t CTL

control

reg32_t IFLS

interrupt fifo level select

reg32_t IMSC

interrupt mask set/clear

reg32_t RIS

raw interrupt status

reg32_t MIS

masked interrupt status

reg32_t ICR

interrupt clear

reg32_t DMACTL

DMA control.