STM32 Nucleo-L073RZ

Support for the STM32 Nucleo-L073RZ.

CLOCK_HSI
1
(16000000U)         /* internal oscillator */
CLOCK_CORECLOCK
1
(32000000U)         /* desired core clock frequency */
CLOCK_PLL_DIV
1
RCC_CFGR_PLLDIV2
CLOCK_PLL_MUL
1
RCC_CFGR_PLLMUL4
CLOCK_AHB_DIV
1
RCC_CFGR_HPRE_DIV1      /* AHB clock -> 32MHz */
CLOCK_APB2_DIV
1
RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 32MHz */
CLOCK_APB1_DIV
1
RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
CLOCK_FLASH_LATENCY
1
FLASH_ACR_LATENCY
CLOCK_AHB
1
(CLOCK_CORECLOCK / 1)
CLOCK_APB2
1
(CLOCK_CORECLOCK / 1)
CLOCK_APB1
1
(CLOCK_CORECLOCK / 1)
const timer_conf_t timer_config()
1
2
3
4
5
6
7
8
9
= {
    {
        .dev      = TIM2,
        .max      = 0x0000ffff,
        .rcc_mask = RCC_APB1ENR_TIM2EN,
        .bus      = APB1,
        .irqn     = TIM2_IRQn
    }
}
TIMER_0_ISR
1
isr_tim2
TIMER_NUMOF
1
(sizeof(timer_config) / sizeof(timer_config[0]))
const uart_conf_t uart_config()
UART_0_ISR
1
(isr_usart2)
UART_1_ISR
1
(isr_usart1)
UART_2_ISR
1
(isr_usart4_5)
UART_NUMOF
1
(sizeof(uart_config) / sizeof(uart_config[0]))
const pwm_conf_t pwm_config()
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
= {
    {
        .dev      = TIM3,
        .rcc_mask = RCC_APB1ENR_TIM3EN,
        .chan     = { { .pin = GPIO_PIN(PORT_B, 4) , .cc_chan = 0 },
                      { .pin = GPIO_PIN(PORT_C, 7) , .cc_chan = 1 },
                      { .pin = GPIO_PIN(PORT_C, 8)         , .cc_chan = 2 },
                      { .pin = GPIO_UNDEF,                   .cc_chan = 0 } },
        .af       = GPIO_AF2,
        .bus      = APB1
    }
}
PWM_NUMOF
1
(sizeof(pwm_config) / sizeof(pwm_config[0]))
const uint8_t spi_divtable()
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
= {
    {       
        7,  
        5,  
        4,  
        2,  
        1   
    },
    {       
        7,  
        5,  
        4,  
        2,  
        1   
    }
}
const spi_conf_t spi_config()
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
= {
    {
        .dev      = SPI1,
        .mosi_pin = GPIO_PIN(PORT_A, 7),
        .miso_pin = GPIO_PIN(PORT_A, 6),
        .sclk_pin = GPIO_PIN(PORT_A, 5),
        .cs_pin   = GPIO_UNDEF,
        .af       = GPIO_AF0,
        .rccmask  = RCC_APB2ENR_SPI1EN,
        .apbbus   = APB2
    }
}
SPI_NUMOF
1
(sizeof(spi_config) / sizeof(spi_config[0]))
ADC_CONFIG
1
2
3
4
5
6
7
8
{            \
    { GPIO_PIN(PORT_A, 0), 0 }, \
    { GPIO_PIN(PORT_A, 1), 1 }, \
    { GPIO_PIN(PORT_A, 4), 4 }, \
    { GPIO_PIN(PORT_B, 0), 8 }, \
    { GPIO_PIN(PORT_C, 1), 11 },\
    { GPIO_PIN(PORT_C, 0), 10 } \
}
ADC_NUMOF
1
(6U)
const i2c_conf_t i2c_config()
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
= {
    {
        .dev            = I2C1,
        .speed          = I2C_SPEED_NORMAL,
        .scl_pin        = GPIO_PIN(PORT_B, 8),
        .sda_pin        = GPIO_PIN(PORT_B, 9),
        .scl_af         = GPIO_AF4,
        .sda_af         = GPIO_AF4,
        .bus            = APB1,
        .rcc_mask       = RCC_APB1ENR_I2C1EN,
        .irqn           = I2C1_IRQn
    },
    {
        .dev            = I2C2,
        .speed          = I2C_SPEED_NORMAL,
        .scl_pin        = GPIO_PIN(PORT_B, 13),
        .sda_pin        = GPIO_PIN(PORT_B, 14),
        .scl_af         = GPIO_AF5,
        .sda_af         = GPIO_AF5,
        .bus            = APB1,
        .rcc_mask       = RCC_APB1ENR_I2C2EN,
        .irqn           = I2C2_IRQn
    }
}
I2C_0_ISR
1
isr_i2c1
I2C_1_ISR
1
isr_i2c2
I2C_NUMOF
1
(sizeof(i2c_config) / sizeof(i2c_config[0]))
RTC_NUMOF
1
(1U)