msp430_regs.h

Cortex CMSIS style definition of MSP430 registers.

This file is incomplete, not all registers are listed. Further There are probably some inconsistencies throughout the MSP430 family which need to be addressed.

REG8

Shortcut to specify 8-bit wide registers. 

1
volatile uint8_t
REG16

Shortcut to specify 16-bit wide registers. 

1
volatile uint16_t
SFR_IE1_OFIE

SFR interrupt enable 1 register bitmap. 

1
(0x02)
SFR_IE1_URXIE0
1
(0x40)
SFR_IE1_UTXIE0
1
(0x80)
SFR_IE2_UCA0RXIE

SFR interrupt enable 2 register bitmap. 

1
(0x01)
SFR_IE2_UCA0TXIE
1
(0x02)
SFR_IE2_URXIE2
1
(0x10)
SFR_IE2_UTXIE2
1
(0x20)
SFR_IFG1_OFIFG

SFR interrupt flag 1 register bitmap. 

1
(0x02)
SFR_IFG1_URXIFG0
1
(0x40)
SFR_IFG1_UTXIFG0
1
(0x80)
SFR_IFG2_UCA0RXIFG

SFR interrupt flag 2 register bitmap. 

1
(0x01)
SFR_IFG2_UCA0TXIFG
1
(0x02)
SFR_IFG2_URXIFG1
1
(0x10)
SFR_IFG2_UTXIFG1
1
(0x20)
SFR_ME1_USPIE0

SFR module enable register 1. 

1
(0x40)
SFR_ME2_USPIE1

SFR module enable register 2. 

1
(0x10)
USART_CTL_SWRST

USART control register bitmap. 

1
(0x01)
USART_CTL_MM
1
(0x02)
USART_CTL_SYNC
1
(0x04)
USART_CTL_LISTEN
1
(0x08)
USART_CTL_CHAR
1
(0x10)
USART_CTL_SPB
1
(0x20)
USART_CTL_PEV
1
(0x40)
USART_CTL_PENA
1
(0x80)
USART_TCTL_TXEPT

USART transmit control register bitmap. 

1
(0x01)
USART_TCTL_STC
1
(0x02)
USART_TCTL_TXWAKE
1
(0x04)
USART_TCTL_URXSE
1
(0x08)
USART_TCTL_SSEL_MASK
1
(0x30)
USART_TCTL_SSEL_UCLKI
1
(0x00)
USART_TCTL_SSEL_ACLK
1
(0x10)
USART_TCTL_SSEL_SMCLK
1
(0x20)
USART_TCTL_CKPL
1
(0x40)
USART_TCTL_CKPH
1
(0x80)
USART_RCTL_RXERR

USART receive control register bitmap. 

1
(0x01)
USART_RCTL_RXWAKE
1
(0x02)
USART_RCTL_URXWIE
1
(0x04)
USART_RCTL_URXEIE
1
(0x08)
USART_RCTL_BRK
1
(0x10)
USART_RCTL_OE
1
(0x20)
USART_RCTL_PE
1
(0x40)
USART_RCTL_FE
1
(0x80)
USCI_ACTL0_UCSYNC

USCI control A register 0 bitmap. 

1
(0x01)
USCI_ACTL0_MODE_MASK
1
(0x06)
USCI_ACTL0_MODE_UART
1
(0x00)
USCI_ACTL0_MODE_ILMM
1
(0x02)
USCI_ACTL0_MODE_ABMM
1
(0x04)
USCI_ACTL0_MODE_UART_ABR
1
(0x06)
USCI_ACTL0_SPB
1
(0x08)
USCI_ACTL0_7BIT
1
(0x10)
USCI_ACTL0_MSB
1
(0x20)
USCI_ACTL0_PAR
1
(0x40)
USCI_ACTL0_PEN
1
(0x80)
USCI_SPI_CTL0_UCSYNC

USCI control register 0 bitmap SPI mode. 

1
(0x01)
USCI_SPI_CTL0_MODE_3
1
(0x06)
USCI_SPI_CTL0_MODE_0
1
(0x00)
USCI_SPI_CTL0_MODE_1
1
(0x02)
USCI_SPI_CTL0_MODE_2
1
(0x04)
USCI_SPI_CTL0_MST
1
(0x08)
USCI_SPI_CTL0_7BIT
1
(0x10)
USCI_SPI_CTL0_MSB
1
(0x20)
USCI_SPI_CTL0_CKPL
1
(0x40)
USCI_SPI_CTL0_CKPH
1
(0x80)
USCI_SPI_STAT_UCBUSY

USCI status register bitmap SPI mode. 

1
(0x01)
USCI_SPI_STAT_UCOE
1
(0x20)
USCI_SPI_STAT_UCFE
1
(0x40)
USCI_SPI_STAT_UCLISTEN
1
(0x80)
USCI_ACTL1_SWRST

USCI control A register 1 bitmap. 

1
(0x01)
USCI_ACTL1_TXBRK
1
(0x02)
USCI_ACTL1_TXADDR
1
(0x04)
USCI_ACTL1_DORM
1
(0x08)
USCI_ACTL1_BRKIE
1
(0x10)
USCI_ACTL1_RXEIE
1
(0x20)
USCI_ACTL1_SSEL_MASK
1
(0xc0)
USCI_ACTL1_SSEL_UCLK
1
(0x00)
USCI_ACTL1_SSEL_ACLK
1
(0x40)
USCI_ACTL1_SSEL_SMCLK
1
(0xc0)
USCI_SPI_CTL1_SWRST

USCI control register 1 bitmap SPI mode. 

1
(0x01)
USCI_SPI_CTL1_SSEL_MASK
1
(0xc0)
USCI_SPI_CTL1_SSEL_NA
1
(0x00)
USCI_SPI_CTL1_SSEL_ACLK
1
(0x40)
USCI_SPI_CTL1_SSEL_SMCLK
1
(0xc0)
USCI_AMCTL_OS16

USCI modulation A control register. 

1
(0x01)
USCI_AMCTL_BRS_MASK
1
(0xe0)
USCI_AMCTL_BRS_SHIFT
1
(1U)
USCI_AMCTL_BRF_MASK
1
(0xf0)
USCI_AMCTL_BRF_SHIFT
1
(4U)
USCI_ASTAT_BUSY

USCI status A register bitmap. 

1
(0x01)
USCI_ASTAT_IDLE
1
(0x02)
USCI_ASTAT_ADDR
1
(0x02)
USCI_ASTAT_RXERR
1
(0x04)
USCI_ASTAT_BRK
1
(0x08)
USCI_ASTAT_PE
1
(0x10)
USCI_ASTAT_OE
1
(0x20)
USCI_ASTAT_FE
1
(0x40)
USCI_ASTAT_LISTEN
1
(0x80)
TIMER_CTL_IFG

Timer Control register bitmap. 

1
(0x0001)
TIMER_CTL_IE
1
(0x0002)
TIMER_CTL_CLR
1
(0x0004)
TIMER_CTL_MC_MASK
1
(0x0030)
TIMER_CTL_MC_STOP
1
(0x0000)
TIMER_CTL_MC_UP
1
(0x0010)
TIMER_CTL_MC_CONT
1
(0x0020)
TIMER_CTL_MC_UPDOWN
1
(0x0030)
TIMER_CTL_ID_MASK
1
(0x00c0)
TIMER_CTL_ID_DIV1
1
(0x0000)
TIMER_CTL_ID_DIV2
1
(0x0040)
TIMER_CTL_ID_DIV4
1
(0x0080)
TIMER_CTL_ID_DIV8
1
(0x00c0)
TIMER_CTL_TASSEL_MASK
1
(0x0300)
TIMER_CTL_TASSEL_TCLK
1
(0x0000)
TIMER_CTL_TASSEL_ACLK
1
(0x0100)
TIMER_CTL_TASSEL_SMCLK
1
(0x0200)
TIMER_CTL_TASSEL_INV_TCLK
1
(0x0300)
TIMER_CCTL_CCIFG

Timer Channel Control register bitmap. 

1
(0x0001)
TIMER_CCTL_COV
1
(0x0002)
TIMER_CCTL_OUT
1
(0x0004)
TIMER_CCTL_CCI
1
(0x0008)
TIMER_CCTL_CCIE
1
(0x0010)
TIMER_CCTL_OUTMOD_MASK
1
(0x00e0)
TIMER_CCTL_OUTMOD_OUTVAL
1
(0x0000)
TIMER_CCTL_OUTMOD_SET
1
(0x0020)
TIMER_CCTL_OUTMOD_TOG_RESET
1
(0x0040)
TIMER_CCTL_OUTMOD_SET_RESET
1
(0x0060)
TIMER_CCTL_OUTMOD_TOGGLE
1
(0x0080)
TIMER_CCTL_OUTMOD_RESET
1
(0x00a0)
TIMER_CCTL_OUTMOD_TOG_SET
1
(0x00c0)
TIMER_CCTL_OUTMOD_RESET_SET
1
(0x00e0)
TIMER_CCTL_CAP
1
(0x0100)
TIMER_CCTL_CLLD_MASK
1
(0x0600)
TIMER_CCTL_SCS
1
(0x0800)
TIMER_CCTL_CCIS_MASK
1
(0x3000)
TIMER_CCTL_CM_MASK
1
(0xc000)
SFR_BASE

Base register address definitions. 

1
((uint16_t)0x0000)
PORT_1_BASE
1
((uint16_t)0x0020)
PORT_2_BASE
1
((uint16_t)0x0028)
PORT_3_BASE
1
((uint16_t)0x0018)
PORT_4_BASE
1
((uint16_t)0x001c)
PORT_5_BASE
1
((uint16_t)0x0030)
PORT_6_BASE
1
((uint16_t)0x0034)
CLK_BASE
1
((uint16_t)0x0053)
USART_0_BASE
1
((uint16_t)0x0070)
USART_1_BASE
1
((uint16_t)0x0078)
TIMER_IVEC_BASE
1
((uint16_t)0x011e)
TIMER_A_BASE
1
((uint16_t)0x0160)
TIMER_B_BASE
1
((uint16_t)0x0180)
WD_BASE
1
((uint16_t)0x0120)
USCI_0_BASE
1
((uint16_t)0x005d)
USCI_0_A_BASE
1
((uint16_t)0x0060)
USCI_0_B_BASE
1
((uint16_t)0x0068)
USCI_1_BASE
1
((uint16_t)0x00cd)
USCI_1_A_BASE
1
((uint16_t)0x00d0)
USCI_1_B_BASE
1
((uint16_t)0x00d8)
SFR

Typing of base register objects. 

1
((msp_sfr_t *)SFR_BASE)
PORT_1
1
((msp_port_t *)PORT_1_BASE)
PORT_2
1
((msp_port_t *)PORT_2_BASE)
PORT_3
1
((msp_port_t *)PORT_3_BASE)
PORT_4
1
((msp_port_t *)PORT_4_BASE)
PORT_5
1
((msp_port_t *)PORT_5_BASE)
PORT_6
1
((msp_port_t *)PORT_6_BASE)
CLK
1
((msp_clk_t *)CLK_BASE)
USART_0
1
((msp_usart_t *)USART_0_BASE)
USART_1
1
((msp_usart_t *)USART_1_BASE)
TIMER_IVEC
1
((msp_timer_ivec_t *)TIMER_IVEC_BASE)
TIMER_A
1
((msp_timer_t *)TIMER_A_BASE)
TIMER_B
1
((msp_timer_t *)TIMER_B_BASE)
WD
1
((msp_wd_t *)WD_BASE)
USCI_0
1
((msp_usci_t *)USCI_0_BASE)
USCI_1
1
((msp_usci_t *)USCI_1_BASE)
USCI_0_A_SPI
1
((msp_usci_spi_t *)USCI_0_A_BASE)
USCI_0_B_SPI
1
((msp_usci_spi_t *)USCI_0_B_BASE)
USCI_1_A
1
((msp_usci_t *)USCI_1_A_BASE)
USCI_1_B
1
((msp_usci_t *)USCI_1_B_BASE)
struct msp_sfr_t

Special function registers.

msp430_regs.h::REG8 IE1

interrupt enable 1

msp430_regs.h::REG8 IE2

interrupt enable 2

msp430_regs.h::REG8 IFG1

interrupt flag 1

msp430_regs.h::REG8 IFG2

interrupt flag 2

msp430_regs.h::REG8 ME1

module enable 1

msp430_regs.h::REG8 ME2

module enable 2

struct msp_port_t

Digital I/O Port w/o interrupt functionality (P3-P6)

msp430_regs.h::REG8 IN

input data

msp430_regs.h::REG8 OD

output data

msp430_regs.h::REG8 DIR

pin direction

msp430_regs.h::REG8 SEL

alternative function select

struct msp_port_isr_t

Digital I/O Port with interrupt functionality (P1 & P2)

msp430_regs.h::REG8 IN

input data

msp430_regs.h::REG8 OD

output data

msp430_regs.h::REG8 DIR

pin direction

msp430_regs.h::REG8 IFG

interrupt flag

msp430_regs.h::REG8 IES

interrupt edge select

msp430_regs.h::REG8 IE

interrupt enable

msp430_regs.h::REG8 SEL

alternative function select

struct msp_usart_t

USART (UART, SPI and I2C) registers.

msp430_regs.h::REG8 CTL

USART control.

msp430_regs.h::REG8 TCTL

transmit control

msp430_regs.h::REG8 RCTL

receive control

msp430_regs.h::REG8 MCTL

modulation control

msp430_regs.h::REG8 BR0

baud rate control 0

msp430_regs.h::REG8 BR1

baud rate control 1

msp430_regs.h::REG8 RXBUF

receive buffer

msp430_regs.h::REG8 TXBUF

transmit buffer

struct msp_usci_t

USCI universal serial control interface registers.

msp430_regs.h::REG8 ABCTL

auto baud rate control

msp430_regs.h::REG8 IRTCTL

IrDA transmit control.

msp430_regs.h::REG8 IRRCTL

IrDA receive control.

msp430_regs.h::REG8 ACTL0

A control 0.

msp430_regs.h::REG8 ACTL1

A control 1.

msp430_regs.h::REG8 ABR0

A baud rate control 0.

msp430_regs.h::REG8 ABR1

A baud rate control 1.

msp430_regs.h::REG8 AMCTL

A modulation control.

msp430_regs.h::REG8 ASTAT

A status.

msp430_regs.h::REG8 ARXBUF

A receive buffer.

msp430_regs.h::REG8 ATXBUF

A transmit buffer.

msp430_regs.h::REG8 BCTL0

B control 0.

msp430_regs.h::REG8 BCTL1

B control 1.

msp430_regs.h::REG8 BBR0

B baud rate 0.

msp430_regs.h::REG8 BBR1

B baud rate 1.

msp430_regs.h::REG8 BI2CIE

I2C interrupt enable.

msp430_regs.h::REG8 BSTAT

B status.

msp430_regs.h::REG8 BRXBUF

B receive buffer.

msp430_regs.h::REG8 BTXBUF

B transmit buffer.

struct msp_usci_spi_t

USCI SPI specific registers.

msp430_regs.h::REG8 CTL0

control 0

msp430_regs.h::REG8 CTL1

control 1

msp430_regs.h::REG8 BR0

baud rate 0

msp430_regs.h::REG8 BR1

baud rate 1

msp430_regs.h::REG8 reserved

reserved

msp430_regs.h::REG8 STAT

status

msp430_regs.h::REG8 RXBUF

receive buffer

msp430_regs.h::REG8 TXBUF

transmit buffer

struct msp_timer_ivec_t

Timer interrupt status registers.

msp430_regs.h::REG16 TBIV

TIMER_A interrupt status.

msp430_regs.h::REG16 reserved()

reserved

msp430_regs.h::REG16 TAIV

TIMER_B interrupt status.

struct msp_timer_t

Timer module registers.

msp430_regs.h::REG16 CTL

timer control

msp430_regs.h::REG16 CCTL()

capture compare channel control

msp430_regs.h::REG16 R

current counter value

msp430_regs.h::REG16 CCR()

capture compare channel values

msp430_regs.h::REG16 reserved()

reserved

msp430_regs.h::REG16 IV

interrupt vector

msp430_regs.h::REG16 EX0

expansion 0