mma8x5x_regs.h

Register definition for the MMA8x5x accelerometer driver.

MMA8X5X_STATUS

Data or FIFO Status. 

1
0x00
MMA8X5X_OUT_X_MSB

[7:0] are 8 MSBs of X data 

1
0x01
MMA8X5X_OUT_X_LSB

[7:4] are 4 LSBs of X data 

1
0x02
MMA8X5X_OUT_Y_MSB

[7:0] are 8 MSBs of Y data 

1
0x03
MMA8X5X_OUT_Y_LSB

[7:4] are 4 LSBs of Y data 

1
0x04
MMA8X5X_OUT_Z_MSB

[7:0] are 8 MSBs of Z data 

1
0x05
MMA8X5X_OUT_Z_LSB

[7:4] are 8 LSBs of Z data 

1
0x06
MMA8X5X_F_SETUP

FIFO setup. 

1
0x09
MMA8X5X_TRIG_CFG

Map of FIFO data capture events. 

1
0x0A
MMA8X5X_SYSMOD

Current System mode. 

1
0x0B
MMA8X5X_INT_SOURCE

Interrupt status. 

1
0x0C
MMA8X5X_WHO_AM_I

Device ID. 

1
0x0D
MMA8X5X_XYZ_DATA_CFG

Dynamic Range Settings. 

1
0x0E
MMA8X5X_HP_FILTER_CUTOFF

High-Pass Filter Selection. 

1
0x0F
MMA8X5X_PL_STATUS

Landscape/Portrait orientation status. 

1
0x10
MMA8X5X_PL_CFG

Landscape/Portrait configuration. 

1
0x11
MMA8X5X_PL_COUNT

Landscape/Portrait debounce counter. 

1
0x12
MMA8X5X_PL_BF_ZCOMP

Back/Front, Z-Lock Trip threshold. 

1
0x13
MMA8X5X_P_L_THS_REG

Portrait/Landscape Threshold and Hysteresis. 

1
0x14
MMA8X5X_FF_MT_CFG

Freefall/Motion functional block configuration. 

1
0x15
MMA8X5X_FF_MT_SRC

Freefall/Motion event source register. 

1
0x16
MMA8X5X_FF_MT_THS

Freefall/Motion threshold register. 

1
0x17
MMA8X5X_FF_MT_COUNT

Freefall/Motion debounce counter. 

1
0x18
MMA8X5X_TRANSIENT_CFG

Transient functional block configuration. 

1
0x1D
MMA8X5X_TRANSIENT_SRC

Transient event status register. 

1
0x1E
MMA8X5X_TRANSIENT_THS

Transient event threshold. 

1
0x1F
MMA8X5X_TRANSIENT_COUNT

Transient debounce counter. 

1
0x20
MMA8X5X_PULSE_CFG

Pulse enable configuration. 

1
0x21
MMA8X5X_PULSE_SRC

Pulse detection source. 

1
0x22
MMA8X5X_PULSE_THSX

X pulse threshold. 

1
0x23
MMA8X5X_PULSE_THSY

Y pulse threshold. 

1
0x24
MMA8X5X_PULSE_THSZ

Z pulse threshold. 

1
0x25
MMA8X5X_PULSE_TMLT

Time limit for pulse. 

1
0x26
MMA8X5X_PULSE_LTCY

Latency time for 2nd pulse. 

1
0x27
MMA8X5X_PULSE_WIND

Window time for 2nd pulse. 

1
0x28
MMA8X5X_ASLP_COUNT

Counter setting for Auto-SLEEP. 

1
0x29
MMA8X5X_CTRL_REG1

Data rates and modes setting. 

1
0x2A
MMA8X5X_CTRL_REG2

Sleep Enable, OS modes, RST, ST. 

1
0x2B
MMA8X5X_CTRL_REG3

Wake from Sleep, IPOL, PP_OD. 

1
0x2C
MMA8X5X_CTRL_REG4

Interrupt enable register. 

1
0x2D
MMA8X5X_CTRL_REG5

Interrupt pin (INT1/INT2) map. 

1
0x2E
MMA8X5X_OFF_X

X-axis offset adjust. 

1
0x2F
MMA8X5X_OFF_Y

Y-axis offset adjust. 

1
0x30
MMA8X5X_OFF_Z

Z-axis offset adjust. 

1
0x31
MMA8X5X_STATUS_XDR

MMA8x5x register bitfields. 

1
(1 << 0)
MMA8X5X_STATUS_YDR
1
(1 << 1)
MMA8X5X_STATUS_ZDR
1
(1 << 2)
MMA8X5X_STATUS_ZYXDR
1
(1 << 3)
MMA8X5X_STATUS_XOW
1
(1 << 4)
MMA8X5X_STATUS_YOW
1
(1 << 5)
MMA8X5X_STATUS_ZOW
1
(1 << 6)
MMA8X5X_STATUS_ZYXOW
1
(1 << 7)
MMA8X5X_F_STATUS_F_CNT_MASK
1
0x3F
MMA8X5X_F_STATUS_F_WMRK_FLAG
1
(1 << 6)
MMA8X5X_F_STATUS_F_OVF
1
(1 << 7)
MMA8X5X_F_SETUP_MODE_MASK
1
0xC0
MMA8X5X_F_SETUP_MODE_DISABLED
1
0
MMA8X5X_F_SETUP_MODE_CIRCULAR
1
1
MMA8X5X_F_SETUP_MODE_STOP
1
2
MMA8X5X_F_SETUP_MODE_TRIGGER
1
3
MMA8X5X_F_SETUP_F_WMRK_MASK
1
0x3F
MMA8X5X_TRIG_CFG_FF_MT
1
(1 << 2)
MMA8X5X_TRIG_CFG_PULSE
1
(1 << 3)
MMA8X5X_TRIG_CFG_LNDPRT
1
(1 << 4)
MMA8X5X_TRIG_CFG_TRANS
1
(1 << 5)
MMA8X5X_SYSMOD_MASK
1
0x3
MMA8X5X_SYSMOD_STANDBY
1
0
MMA8X5X_SYSMOD_WAKE
1
1
MMA8X5X_SYSMOD_SLEEP
1
2
MMA8X5X_SYSMOD_FGT_MASK
1
0x7C
MMA8X5X_SYSMOD_FGERR
1
(1 << 7)
MMA8X5X_INT_SOURCE_DRDY
1
(1 << 0)
MMA8X5X_INT_SOURCE_FF_MT
1
(1 << 2)
MMA8X5X_INT_SOURCE_PULSE
1
(1 << 3)
MMA8X5X_INT_SOURCE_LNDPRT
1
(1 << 4)
MMA8X5X_INT_SOURCE_TRANS
1
(1 << 5)
MMA8X5X_INT_SOURCE_FIFO
1
(1 << 6)
MMA8X5X_INT_SOURCE_ASLP
1
(1 << 7)
MMA8X5X_XYZ_DATA_CFG_FS_MASK
1
0x3
MMA8X5X_XYZ_DATA_CFG_HPF_OUT
1
(1 << 4)
MMA8X5X_HP_FILTER_SEL_MASK
1
0x03
MMA8X5X_HP_FILTER_LPF_EN
1
(1 << 4)
MMA8X5X_HP_FILTER_HPF_BYP
1
(1 << 5)
MMA8X5X_PL_STATUS_BAFRO
1
(1 << 0)
MMA8X5X_PL_STATUS_LAPO_MASK
1
0x6
MMA8X5X_PL_STATUS_LAPO_P_UP
1
0
MMA8X5X_PL_STATUS_LAPO_P_DOWN
1
1
MMA8X5X_PL_STATUS_LAPO_L_RIGHT
1
2
MMA8X5X_PL_STATUS_LAPO_L_LEFT
1
3
MMA8X5X_PL_STATUS_LO
1
(1 << 6)
MMA8X5X_PL_STATUS_NEWLP
1
(1 << 7)
MMA8X5X_PL_CFG_PL_EN
1
(1 << 6)
MMA8X5X_PL_CFG_DBCNTM
1
(1 << 7)
MMA8X5X_PL_BF_ZCOMP_ZLOCK_MASK
1
0x07
MMA8X5X_PL_BF_ZCOMP_BKFR_MASK
1
0xC0
MMA8X5X_P_L_HYS_MASK
1
0x07
MMA8X5X_P_L_THS_MASK
1
0xF8
MMA8X5X_FF_MT_CFG_XEFE
1
(1 << 3)
MMA8X5X_FF_MT_CFG_YEFE
1
(1 << 4)
MMA8X5X_FF_MT_CFG_ZEFE
1
(1 << 5)
MMA8X5X_FF_MT_CFG_OAE
1
(1 << 6)
MMA8X5X_FF_MT_CFG_ELE
1
(1 << 7)
MMA8X5X_FF_MT_SRC_XHP
1
(1 << 0)
MMA8X5X_FF_MT_SRC_XHE
1
(1 << 1)
MMA8X5X_FF_MT_SRC_YHP
1
(1 << 2)
MMA8X5X_FF_MT_SRC_YHE
1
(1 << 3)
MMA8X5X_FF_MT_SRC_ZHP
1
(1 << 4)
MMA8X5X_FF_MT_SRC_ZHE
1
(1 << 5)
MMA8X5X_FF_MT_SRC_EA
1
(1 << 7)
MMA8X5X_FF_MT_THS_MASK
1
0x7F
MMA8X5X_FF_MT_THS_DBCNTM
1
(1 << 7)
MMA8X5X_TRANSIENT_CFG_HPF_BYP
1
(1 << 0)
MMA8X5X_TRANSIENT_CFG_XTEFE
1
(1 << 1)
MMA8X5X_TRANSIENT_CFG_YTEFE
1
(1 << 2)
MMA8X5X_TRANSIENT_CFG_ZTEFE
1
(1 << 3)
MMA8X5X_TRANSIENT_CFG_ELE
1
(1 << 4)
MMA8X5X_TRANSIENT_SRC_XTPOL
1
(1 << 0)
MMA8X5X_TRANSIENT_SRC_XTEVENT
1
(1 << 1)
MMA8X5X_TRANSIENT_SRC_YTPOL
1
(1 << 2)
MMA8X5X_TRANSIENT_SRC_YTEVENT
1
(1 << 3)
MMA8X5X_TRANSIENT_SRC_ZTPOL
1
(1 << 4)
MMA8X5X_TRANSIENT_SRC_ZTEVENT
1
(1 << 5)
MMA8X5X_TRANSIENT_SRC_EA
1
(1 << 6)
MMA8X5X_TRANSIENT_THS_MASK
1
0x7F
MMA8X5X_TRANSIENT_THS_DBCNTM
1
(1<< 7)
MMA8X5X_PULSE_CFG_XSPEFE
1
(1 << 0)
MMA8X5X_PULSE_CFG_XDPEFE
1
(1 << 1)
MMA8X5X_PULSE_CFG_YSPEFE
1
(1 << 2)
MMA8X5X_PULSE_CFG_YDPEFE
1
(1 << 3)
MMA8X5X_PULSE_CFG_ZSPEFE
1
(1 << 4)
MMA8X5X_PULSE_CFG_ZDPEFE
1
(1 << 5)
MMA8X5X_PULSE_CFG_ELE
1
(1 << 6)
MMA8X5X_PULSE_CFG_DPA
1
(1 << 7)
MMA8X5X_PULSE_SRC_POLX
1
(1 << 0)
MMA8X5X_PULSE_SRC_POLY
1
(1 << 1)
MMA8X5X_PULSE_SRC_POLZ
1
(1 << 2)
MMA8X5X_PULSE_SRC_DPE
1
(1 << 3)
MMA8X5X_PULSE_SRC_AXX
1
(1 << 4)
MMA8X5X_PULSE_SRC_AXY
1
(1 << 5)
MMA8X5X_PULSE_SRC_AXZ
1
(1 << 6)
MMA8X5X_PULSE_SRC_EA
1
(1 << 7)
MMA8X5X_PULSE_THSX_MASK
1
0x7F
MMA8X5X_PULSE_THSY_MASK
1
0x7F
MMA8X5X_PULSE_THSZ_MASK
1
0x7F
MMA8X5X_CTRL_REG1_ACTIVE
1
(1 << 0)
MMA8X5X_CTRL_REG1_F_READ
1
(1 << 1)
MMA8X5X_CTRL_REG1_DR_MASK
1
0x38
MMA8X5X_CTRL_REG1_DR_SHIFT
1
3
MMA8X5X_CTRL_REG1_DR( x)
1
2
(((uint8_t)(((uint8_t)(x))<<MMA8X5X_CTRL_REG1_DR_SHIFT))\
                                            &MMA8X5X_CTRL_REG1_DR_MASK)
MMA8X5X_CTRL_REG1_ASR_MASK
1
0xC0
MMA8X5X_CTRL_REG1_ASR_50HZ
1
0
MMA8X5X_CTRL_REG1_ASR_12HZ5
1
1
MMA8X5X_CTRL_REG1_ASR_6HZ25
1
2
MMA8X5X_CTRL_REG1_ASR_1HZ56
1
3
MMA8X5X_CTRL_REG2_MODS_MASK
1
0x3
MMA8X5X_CTRL_REG2_MODS_NORMAL
1
0
MMA8X5X_CTRL_REG2_MODS_LNLP
1
1
MMA8X5X_CTRL_REG2_MODS_HR
1
2
MMA8X5X_CTRL_REG2_MODS_LP
1
3
MMA8X5X_CTRL_REG2_SLPE
1
(1 << 2)
MMA8X5X_CTRL_REG2_SMODS_MASK
1
0x18
MMA8X5X_CTRL_REG2_SMODS_NORMAL
1
0
MMA8X5X_CTRL_REG2_SMODS_LNLP
1
1
MMA8X5X_CTRL_REG2_SMODS_HR
1
2
MMA8X5X_CTRL_REG2_SMODS_LP
1
3
MMA8X5X_CTRL_REG2_RST
1
(1 << 6)
MMA8X5X_CTRL_REG2_ST
1
(1 << 7)
MMA8X5X_CTRL_REG3_PP_OD
1
(1 << 0)
MMA8X5X_CTRL_REG3_IPOL
1
(1 << 1)
MMA8X5X_CTRL_REG3_WAKE_FF_MT
1
(1 << 3)
MMA8X5X_CTRL_REG3_WAKE_PULSE
1
(1 << 4)
MMA8X5X_CTRL_REG3_WAKE_LNDPRT
1
(1 << 5)
MMA8X5X_CTRL_REG3_WAKE_TRANS
1
(1 << 6)
MMA8X5X_CTRL_REG3_FIFO_GATE
1
(1 << 7)
MMA8X5X_CTRL_REG4_INT_EN_DRDY
1
(1 << 0)
MMA8X5X_CTRL_REG4_INT_EN_FF_MT
1
(1 << 2)
MMA8X5X_CTRL_REG4_INT_EN_PULSE
1
(1 << 3)
MMA8X5X_CTRL_REG4_INT_EN_LNDPRT
1
(1 << 4)
MMA8X5X_CTRL_REG4_INT_EN_TRANS
1
(1 << 5)
MMA8X5X_CTRL_REG4_INT_EN_FIFO
1
(1 << 6)
MMA8X5X_CTRL_REG4_INT_EN_ASLP
1
(1 << 7)
MMA8X5X_CTRL_REG5_INT_CFG_DRDY
1
(1 << 0)
MMA8X5X_CTRL_REG5_INT_CFG_FF_MT
1
(1 << 2)
MMA8X5X_CTRL_REG5_INT_CFG_PULSE
1
(1 << 3)
MMA8X5X_CTRL_REG5_INT_CFG_LNDPRT
1
(1 << 4)
MMA8X5X_CTRL_REG5_INT_CFG_TRANS
1
(1 << 5)
MMA8X5X_CTRL_REG5_INT_CFG_FIFO
1
(1 << 6)
MMA8X5X_CTRL_REG5_INT_CFG_ASLP
1
(1 << 7)