lpc2387.h¶
-
IMSEC
¶ 1
0x00000001
-
IMMIN
¶ 1
0x00000002
-
IMHOUR
¶ 1
0x00000004
-
IMDOM
¶ 1
0x00000008
-
IMDOW
¶ 1
0x00000010
-
IMDOY
¶ 1
0x00000020
-
IMMON
¶ 1
0x00000040
-
IMYEAR
¶ 1
0x00000080
-
AMRSEC
¶ 1
0x00000001 /* Alarm mask for Seconds */
-
AMRMIN
¶ 1
0x00000002 /* Alarm mask for Minutes */
-
AMRHOUR
¶ 1
0x00000004 /* Alarm mask for Hours */
-
AMRDOM
¶ 1
0x00000008 /* Alarm mask for Day of Month */
-
AMRDOW
¶ 1
0x00000010 /* Alarm mask for Day of Week */
-
AMRDOY
¶ 1
0x00000020 /* Alarm mask for Day of Year */
-
AMRMON
¶ 1
0x00000040 /* Alarm mask for Month */
-
AMRYEAR
¶ 1
0x00000080 /* Alarm mask for Year */
-
ILR_RTCCIF
¶ 1
BIT0
-
ILR_RTCALF
¶ 1
BIT1
-
ILR_RTSSF
¶ 1
BIT2
-
CCR_CLKEN
¶ 1
0x01
-
CCR_CTCRST
¶ 1
0x02
-
CCR_CLKSRC
¶ 1
0x10
-
WDEN
¶ 1
BIT0
-
WDRESET
¶ 1
BIT1
-
WDTOF
¶ 1
BIT2
-
WDINT
¶ 1
BIT3
-
EXTWAKE0
¶ 1
BIT0
-
EXTWAKE1
¶ 1
BIT1
-
EXTWAKE2
¶ 1
BIT2
-
EXTWAKE3
¶ 1
BIT3
-
ETHWAKE
¶ 1
BIT4
-
USBWAKE
¶ 1
BIT5
-
CANWAKE
¶ 1
BIT6
-
GPIO0WAKE
¶ 1
BIT7
-
GPIO2WAKE
¶ 1
BIT8
-
BODWAKE
¶ 1
BIT14
-
RTCWAKE
¶ 1
BIT15
-
ULSR_RDR
¶ 1
BIT0
-
ULSR_OE
¶ 1
BIT1
-
ULSR_PE
¶ 1
BIT2
-
ULSR_FE
¶ 1
BIT3
-
ULSR_BI
¶ 1
BIT4
-
ULSR_THRE
¶ 1
BIT5
-
ULSR_TEMT
¶ 1
BIT6
-
ULSR_RXFE
¶ 1
BIT7
-
UIIR_INT_STATUS
¶ Interrupt Status.
1
(BIT0)
-
UIIR_THRE_INT
¶ Transmit Holding Register Empty.
1
(BIT1)
-
UIIR_RDA_INT
¶ Receive Data Available.
1
(BIT2)
-
UIIR_RLS_INT
¶ Receive Line Status.
1
(BIT1 | BIT2)
-
UIIR_CTI_INT
¶ Character Timeout Indicator.
1
(BIT2 | BIT3)
-
UIIR_ID_MASK
¶ 1
(BIT1 | BIT2 | BIT3)
-
UIIR_ABEO_INT
¶ 1
BIT8
-
UIIR_ABTO_INT
¶ 1
BIT9
-
SSPSR_TFE
¶ Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
1
BIT0
-
SSPSR_TNF
¶ Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
1
BIT1
-
SSPSR_RNE
¶ Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
1
BIT2
-
SSPSR_RFF
¶ Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
1
BIT3
-
SSPSR_BSY
¶ Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
1
BIT4
-
TXIR
¶ 1
0x00
-
TXTCR
¶ 1
0x04
-
TXTC
¶ Timer counter.
1
0x08
-
TXPR
¶ 1
0x0C
-
TXPC
¶ 1
0x10
-
TXMCR
¶ 1
0x14
-
TXMR0
¶ 1
0x18
-
TXMR1
¶ 1
0x1C
-
TXMR2
¶ 1
0x20
-
TXMR3
¶ 1
0x24
-
TXCCR
¶ 1
0x28
-
TXCR0
¶ 1
0x2C
-
TXCR1
¶ 1
0x30
-
TXCR2
¶ 1
0x34
-
TXCR3
¶ 1
0x38
-
TXEMR
¶ 1
0x3C
-
TXCTCR
¶ 1
0x70
-
F_CCO
¶ 1
288000000
-
CL_CPU_DIV
¶ CPU clock divider.
1
4
-
F_RC_OSCILLATOR
¶ Frequency of internal RC oscillator.
1
4000000
-
F_RTC_OSCILLATOR
¶ Frequency of RTC oscillator.
1
32767
-
VIC_SIZE
¶ 1
32
-
GPIO_INT
¶ 1
17
-
IRQP_GPIO
¶ 1
4
-
_XTAL
¶ 1
(72000)