clk_conf.h

ALT_48MHZ_NO
1
0
ALT_48MHZ_I2S
1
1
ALT_48MHZ_SAI
1
2
ALT_48MHZ_Q
1
0
ALT_48MHZ_P
1
4
enum fam
STM32F0
STM32F1
STM32F2
STM32F3
STM32F4
STM32F7
FAM_MAX
enum @81
STM32F030
STM32F070
STM32F031
STM32F051
STM32F071
STM32F091
STM32F042
STM32F072
STM32F038
STM32F048
STM32F058
STM32F078
STM32F098
STM32F100
STM32F101
STM32F102
STM32F103
STM32F205
STM32F207
STM32F215
STM32F217
STM32F301
STM32F302
STM32F303
STM32F334
STM32F373
STM32F318
STM32F328
STM32F358
STM32F378
STM32F398
STM32F401
STM32F405
STM32F407
STM32F410
STM32F411
STM32F412
STM32F413
STM32F415
STM32F417
STM32F423
STM32F427
STM32F429
STM32F437
STM32F439
STM32F446
STM32F469
STM32F479
STM32F722
STM32F732
STM32F746
STM32F756
STM32F767
STM32F769
STM32F777
STM32F779
MODEL_MAX
STM32F( x)
1
[STM32F##x] = x
STM32F0( x)
1
[STM32F0##x] = x
stm32f2_4_192_pll_cfg

STM32F2xx / STM32F401 PLL config. 

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
{ \
    .min_vco_input = 1000000U, \
    .max_vco_input = 2000000U, \
    .min_vco_output = 192000000U, \
    .max_vco_output = 432000000U, \
    .min_n = 50, \
    .max_n = 432, \
    .inc_n = 1, \
    .min_m = 2, \
    .max_m = 63, \
    .inc_m = 1, \
    .min_p = 2, \
    .max_p = 8, \
    .inc_p = 2, \
    .min_q = 2, \
    .max_q = 15, \
    .inc_q = 1, \
}
stm32f4_7_pll_cfg

STM32F4 (except 401) / STM32F7 PLL config. 

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
{ \
    .min_vco_input = 1000000U, \
    .max_vco_input = 2000000U, \
    .min_vco_output = 192000000U, \
    .max_vco_output = 432000000U, \
    .min_n = 50, \
    .max_n = 432, \
    .inc_n = 1, \
    .min_m = 2, \
    .max_m = 63, \
    .inc_m = 1, \
    .min_p = 2, \
    .max_p = 8, \
    .inc_p = 2, \
    .min_q = 2, \
    .max_q = 15, \
    .inc_q = 1, \
}
const unsigned stm32_model()

List of supported models.

const clk_cfg_t stm32_clk_cfg()

Clock config for supported cpu.

struct pll_cfg_t

PLL configuration parameters.

PLL configuration follows the model: 

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
pll_in  +----+  vco_in  +------------------------------+
--------| /M |----------|\  +----+ vco_out     +----+  |
        +----+          | --| xN |-------------| /P |--|-- pll_p_out
                        |   +----+         \   +----+  |
                        |                   |  +----+  |
                        |                   ---| /Q |--|-- pll_q_out
                        |                   |  +----+  |
                        |                   |  +----+  |
                        |                   ---| /R |--|-- pll_r_out
                        |                      +----+  |
                        +------------------------------+

vco_in = pll_in / M; vco_out = vco_in * N; pll_p_out = vco_out / P; pll_q_out = vco_out / Q; pll_r_out = vco_out / R;

unsigned min_vco_input

Min VCO input.

unsigned max_vco_input

Max VCO input.

unsigned min_vco_output

Min VCO output.

unsigned max_vco_output

Max VCO output.

unsigned min_n

Min N.

unsigned max_n

Max N.

unsigned inc_n

Increment between two values of N.

unsigned min_m

Min M.

unsigned max_m

Max M.

unsigned inc_m

Increment between two values of M.

unsigned min_p

Min P.

unsigned max_p

Max P.

unsigned inc_p

Increment between two values of P.

unsigned min_q

Min Q.

unsigned max_q

Max Q.

unsigned inc_q

Increment between two values of Q.

struct clk_cfg_t

Clock configuration.

enum fam family

Family.

unsigned max_coreclock

Max coreclock.

unsigned max_apb1

Max APB1 clock.

unsigned max_apb2

Max APB2 clock.

unsigned hsi

HSI frequency.

pll_cfg_t pll

PLL configuration.

bool has_pll_i2s

PLL I2S available.

bool has_pll_sai

PLL SAI available.

bool has_pll_i2s_m

PLL I2S has a M factor.

bool has_pll_sai_m

PLL SAI has a M factor.

bool has_pll_i2s_alt_input

PLL I2S has an external input available.

unsigned hsi_prediv

Value if HSI has a fixed prediv, 0 otherwise.

int has_alt_48MHz

48MHz can be generated by an alternate source

bool need_48MHz

48MHz is needed