cc430_regs.h

Cortex CMSIS style definition of CC430 registers.

This file is incomplete, not all registers are listed. Further There are probably some inconsistencies throughout the MSP430 family which need to be addressed.

REG8

Shortcut to specify 8-bit wide registers.

1
volatile uint8_t
REG16

Shortcut to specify 16-bit wide registers.

1
volatile uint16_t
CTL_IFG

Timer Control register bitmap.

1
(0x0001)
CTL_IE
1
(0x0002)
CTL_CLR
1
(0x0004)
CTL_MC_MASK
1
(0x0030)
CTL_MC_STOP
1
(0x0000)
CTL_MC_UP
1
(0x0010)
CTL_MC_CONT
1
(0x0020)
CTL_MC_UPDOWN
1
(0x0030)
CTL_ID_MASK
1
(0x00c0)
CTL_ID_DIV1
1
(0x0000)
CTL_ID_DIV2
1
(0x0040)
CTL_ID_DIV4
1
(0x0080)
CTL_ID_DIV8
1
(0x00c0)
CTL_TASSEL_MASK
1
(0x0300)
CTL_TASSEL_TCLK
1
(0x0000)
CTL_TASSEL_ACLK
1
(0x0100)
CTL_TASSEL_SMCLK
1
(0x0200)
CTL_TASSEL_INV_TCLK
1
(0x0300)
CCTL_CCIFG

Timer Channel Control register bitmap.

1
(0x0001)
CCTL_COV
1
(0x0002)
CCTL_OUT
1
(0x0004)
CCTL_CCI
1
(0x0008)
CCTL_CCIE
1
(0x0010)
CCTL_OUTMOD_MASK
1
(0x00e0)
CCTL_OUTMOD_OUTVAL
1
(0x0000)
CCTL_OUTMOD_SET
1
(0x0020)
CCTL_OUTMOD_TOG_RESET
1
(0x0040)
CCTL_OUTMOD_SET_RESET
1
(0x0060)
CCTL_OUTMOD_TOGGLE
1
(0x0080)
CCTL_OUTMOD_RESET
1
(0x00a0)
CCTL_OUTMOD_TOG_SET
1
(0x00c0)
CCTL_OUTMOD_RESET_SET
1
(0x00e0)
CCTL_CAP
1
(0x0100)
CCTL_CLLD_MASK
1
(0x0600)
CCTL_SCS
1
(0x0800)
CCTL_CCIS_MASK
1
(0x3000)
CCTL_CM_MASK
1
(0xc000)
TIMER_A0_BASE

Base register address definitions.

1
((uint16_t)0x0340)
TIMER_A1_BASE
1
((uint16_t)0x0380)
TIMER_A0

Typing of base register objects.

1
((msp_timer_t *)TIMER_A0_BASE)
TIMER_A1
1
((msp_timer_t *)TIMER_A1_BASE)
struct msp_timer_t

Timer module registers.

msp430_regs.h::REG16 CTL

timer control

msp430_regs.h::REG16 CCTL()

capture compare channel control

msp430_regs.h::REG16 R

current counter value

msp430_regs.h::REG16 CCR()

capture compare channel values

msp430_regs.h::REG16 reserved()

reserved

msp430_regs.h::REG16 IV

interrupt vector

msp430_regs.h::REG16 EX0

expansion 0