cc26x0_gpt.h

definitions for the CC26x0 GPT moduls

GPT0_BASE

GPT base register addresses. 

1
(0x40010000)

GTP0 base address

GPT1_BASE

GTP1 base address. 

1
(0x40011000)
GPT2_BASE

GTP2 base address. 

1
(0x40012000)
GPT3_BASE

GTP3 base address. 

1
(0x40013000)
GPT0

GPT instances. 

1
((gpt_reg_t *) (GPT0_BASE))
GPT1
1
((gpt_reg_t *) (GPT1_BASE))
GPT2
1
((gpt_reg_t *) (GPT2_BASE))
GPT3
1
((gpt_reg_t *) (GPT3_BASE))
GPT_CFG_32T

GPT register values. 

1
0
GPT_CFG_32RTC
1
1
GPT_CFG_16T
1
4
GPT_TXMR_TXMR_ONE_SHOT
1
0x00000001
GPT_TXMR_TXMR_PERIODIC
1
0x00000002
GPT_TXMR_TXMR_CAPTURE
1
0x00000003
GPT_TXMR_TXCM_EDGECNT
1
0x00000000
GPT_TXMR_TXCM_EDGETIME
1
0x00000004
GPT_TXMR_TXAMS_CAPTCOMP
1
0x00000000
GPT_TXMR_TXAMS_PWM
1
0x00000008
GPT_TXMR_TXCDIR_DOWN
1
0x00000000
GPT_TXMR_TXCDIR_UP
1
0x00000010 /* starts from 0 */
GPT_TXMR_TXMIE
1
0x00000020 /* match interrupt */
GPT_TXMR_TXWOT
1
0x00000040 /* wait on trigger from daisy */
GPT_TXMR_TXSNAPS
1
0x00000080
GPT_TXMR_TXILD_CLOCK
1
0x00000000 /* interrupt loac: update TXPR or TXR */
GPT_TXMR_TXILD_TIMEOUT
1
0x00000100
GPT_TXMR_TXPWMIE
1
0x00000200
GPT_TXMR_TXMRSU
1
0x00000400
GPT_TXMR_TXPLO
1
0x00000800
GPT_TXMR_TXCIN
1
0x00001000
GPT_TXMR_TCACT_DIS
1
0x00000000
GPT_TXMR_TCACT_TGL_TO
1
0x00002000
GPT_TXMR_TCACT_CLR_TO
1
0x00004000
GPT_TXMR_TCACT_SET_TO
1
0x00006000
GPT_TXMR_TCACT_SET_NOW_TGL_TO
1
0x00008000
GPT_TXMR_TCACT_CLR_NOW_TGL_TO
1
0x0000a000
GPT_TXMR_TCACT_SET_NOW_CLR_TO
1
0x0000c000
GPT_TXMR_TCACT_CLR_NOW_SET_TO
1
0x0000e000
GPT_CTL_TAEN
1
0x00000001
GPT_CTL_TASTALL
1
0x00000002
GPT_CTL_TAEVENT_POS
1
0x00000000
GPT_CTL_TAEVENT_NEG
1
0x00000004
GPT_CTL_TAEVENT_BOTH
1
0x0000000c
GPT_CTL_RTCEN
1
0x00000010
GPT_CTL_TAPWML_INV
1
0x00000040
GPT_CTL_TBEN
1
0x00000100 /* still need capture CFG */
GPT_CTL_TBSTALL
1
0x00000200
GPT_CTL_TBEVENT_POS
1
0x00000000
GPT_CTL_TBEVENT_NEG
1
0x00000400
GPT_CTL_TBEVENT_BOTH
1
0x00000c00
GPT_CTL_TBPWML_INV
1
0x00004000
GPT_SYNC_SYNC1_A
1
0x00000001
GPT_SYNC_SYNC1_B
1
0x00000002
GPT_SYNC_SYNC2_A
1
0x00000004
GPT_SYNC_SYNC2_B
1
0x00000008
GPT_SYNC_SYNC3_A
1
0x00000010
GPT_SYNC_SYNC3_B
1
0x00000020
GPT_SYNC_SYNC4_A
1
0x00000040
GPT_SYNC_SYNC4_B
1
0x00000080
GPT_IMR_TATOIM
1
0x00000001
GPT_IMR_CAMIM
1
0x00000002
GPT_IMR_CAEIM
1
0x00000004
GPT_IMR_RTCIM
1
0x00000008
GPT_IMR_TAMIM
1
0x00000010
GPT_IMR_DMAAIM
1
0x00000020
GPT_IMR_TBTOIM
1
0x00000100
GPT_IMR_CBMIM
1
0x00000200
GPT_IMR_CBEIM
1
0x00000400
GPT_IMR_TBMIM
1
0x00000800
GPT_IMR_DMABIM
1
0x00002000
GPT_IMR_WUMIS
1
0x00010000
GPT_RIS_TATORIS
1
0x00000001
GPT_RIS_CAMRIS
1
0x00000002
GPT_RIS_CAERIS
1
0x00000004
GPT_RIS_RTCRIS
1
0x00000008
GPT_RIS_TAMRIS
1
0x00000010
GPT_RIS_TBTORIS
1
0x00000100
GPT_RIS_CBMRIS
1
0x00000200
GPT_RIS_CBERIS
1
0x00000400
GPT_RIS_TBMRIS
1
0x00000800
GPT_RIS_DMARIS
1
0x00002000
GPT_RIS_WURIS
1
0x00010000
GPT_MIS_TATOMIS
1
0x00000001
GPT_MIS_CAMMIS
1
0x00000002
GPT_MIS_CAEMIS
1
0x00000004
GPT_MIS_RTCMIS
1
0x00000008
GPT_MIS_TAMMIS
1
0x00000010
GPT_MIS_TBTOMIS
1
0x00000100
GPT_MIS_CBMMIS
1
0x00000200
GPT_MIS_CBEMIS
1
0x00000400
GPT_MIS_TBMMIS
1
0x00000800
GPT_MIS_DMAMIS
1
0x00002000
GPT_MIS_WUMIS
1
0x00010000
GPT_ICLR_TATOCINT
1
0x00000001
GPT_ICLR_CAMCINT
1
0x00000002
GPT_ICLR_CAECINT
1
0x00000004
GPT_ICLR_RTCCINT
1
0x00000008
GPT_ICLR_TAMCINT
1
0x00000010
GPT_ICLR_TBTOCINT
1
0x00000100
GPT_ICLR_CBMCINT
1
0x00000200
GPT_ICLR_CBECINT
1
0x00000400
GPT_ICLR_TBMCINT
1
0x00000800
GPT_ICLR_DMACINT
1
0x00002000
GPT_ICLR_WUCINT
1
0x00010000
GPT_DMAEV_TATODMAEN
1
0x00000001
GPT_DMAEV_CAMDMAEN
1
0x00000002
GPT_DMAEV_CAEDMAEN
1
0x00000004
GPT_DMAEV_RTCDMAEN
1
0x00000008
GPT_DMAEV_TAMDMAEN
1
0x00000010
GPT_DMAEV_TBTODMAEN
1
0x00000100
GPT_DMAEV_CBMDMAEN
1
0x00000200
GPT_DMAEV_CBEDMAEN
1
0x00000400
GPT_DMAEV_TBMDMAEN
1
0x00000800
GPT_NUMOF

GPT count. 

1
4
NUM_CHANNELS_PER_GPT

GPT channel count. 

1
1
struct gpt_reg_t

GPT registers.

reg32_t CFG

config

reg32_t TAMR

timer A mode

reg32_t TBMR

timer B mode

reg32_t CTL

control

reg32_t SYNC

sync timers

reg32_t __reserved1

unused

reg32_t IMR

interrupt mask register

reg32_t RIS

raw interrupt status

reg32_t MIS

masked interrupt status

reg32_t ICLR

interrupt clear

reg32_t TAILR

timer A interval load register

reg32_t TBILR

timer B interval load register

reg32_t TAMATCHR

timer A match register

reg32_t TBMATCHR

timer B match register

reg32_t TAPR

timer A pre-scale

reg32_t TBPR

timer B pre-scale

reg32_t TAPMR

timer A pre-scale match register

reg32_t TBPMR

timer B pre-scale match register

reg32_t TAR

timer A register

reg32_t TBR

timer B register

reg32_t TAV

timer A value

reg32_t TBV

timer B value

reg32_t RTCPD

config

reg32_t TAPS

config

reg32_t TBPS

config

reg32_t TAPV

config

reg32_t TBPV

config

reg32_t DMAEV

config

reg32_t __reserved2()

config

reg32_t VERSION

config

reg32_t ANDCCP

config