boards/nucleo-f031k6/include/periph_conf.h¶
Peripheral MCU configuration for the nucleo-f031k6 board.
-
CLOCK_CORECLOCK
¶ 1
(48000000U)
-
CLOCK_HSE
¶ 1
(0U)
-
CLOCK_LSE
¶ 1
(0)
-
CLOCK_AHB_DIV
¶ 1
RCC_CFGR_HPRE_DIV1
-
CLOCK_AHB
¶ 1
(CLOCK_CORECLOCK / 1)
-
CLOCK_APB1_DIV
¶ 1
RCC_CFGR_PPRE_DIV1 /* max 48MHz */
-
CLOCK_APB1
¶ 1
(CLOCK_CORECLOCK / 1)
-
CLOCK_APB2
¶ 1
(CLOCK_APB1)
-
CLOCK_PLL_PREDIV
¶ 1
(2)
-
CLOCK_PLL_MUL
¶ 1
(12)
-
TIMER_0_ISR
¶ 1
isr_tim2
-
TIMER_NUMOF
¶ 1
(sizeof(timer_config) / sizeof(timer_config[0]))
-
const timer_conf_t
timer_config
()¶ 1 2 3 4 5 6 7 8 9
= { { .dev = TIM2, .max = 0xffffffff, .rcc_mask = RCC_APB1ENR_TIM2EN, .bus = APB1, .irqn = TIM2_IRQn } }
-
UART_0_ISR
¶ 1
(isr_usart1)
-
UART_NUMOF
¶ 1
(sizeof(uart_config) / sizeof(uart_config[0]))
-
const uart_conf_t
uart_config
()¶ 1 2 3 4 5 6 7 8 9 10 11 12
= { { .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_A, 15), .tx_pin = GPIO_PIN(PORT_A, 2), .rx_af = GPIO_AF1, .tx_af = GPIO_AF1, .bus = APB2, .irqn = USART1_IRQn } }
-
PWM_NUMOF
¶ 1
(sizeof(pwm_config) / sizeof(pwm_config[0]))
-
const pwm_conf_t
pwm_config
()¶
-
SPI_NUMOF
¶ 1
(sizeof(spi_config) / sizeof(spi_config[0]))
-
const uint8_t
spi_divtable
()¶ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
= { { 7, 6, 5, 2, 1 }, { 7, 6, 5, 2, 1 } }
-
const spi_conf_t
spi_config
()¶ 1 2 3 4 5 6 7 8 9 10 11 12
= { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_B, 5), .miso_pin = GPIO_PIN(PORT_B, 4), .sclk_pin = GPIO_PIN(PORT_B, 3), .cs_pin = GPIO_UNDEF, .af = GPIO_AF0, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2 } }
-
RTC_NUMOF
¶ Nucleo-f031 does not have any LSE, current RTC driver does not support LSI as clock source, so disabling RTC.
1
(0U)
-
ADC_CONFIG
¶ 1 2 3 4 5 6 7
{ \ { GPIO_PIN(PORT_A, 0), 0 }, \ { GPIO_PIN(PORT_A, 1), 1 }, \ { GPIO_PIN(PORT_A, 3), 3 }, \ { GPIO_PIN(PORT_A, 4), 4 }, \ { GPIO_PIN(PORT_A, 7), 7 } \ }
-
ADC_NUMOF
¶ 1
(5)